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LMK04610: Phase Relation between Input and Output

HeHa
Prodigy 20 points
Part Number: LMK04610

Is the phase between CLKin0 to OSCout or Clkoutx deterministic? In our setup Clkin0 would be a 80 MHz signal as well as the OSCout and relevant CLKoutx.

  • 0
    TI__Mastermind 28960 points

    Hi HeHa,

    If PLL1 is used with the VCXO, CLKinX should always have a deterministic relationship with OSCout because OSCout is a buffered copy of the feedback path to PLL1. For both PLLs, you can configure the zero-delay mode to ensure a deterministic relationship between CLKinX and CLKoutX. In distribution mode, the phase offset is a function of the frequency, since the delay from CLKinX to CLKoutX or to OSCout is an absolute value.

    Deterministic phase, in this case, means that there is a fixed collection of possible phase offsets which can ever be observed between CLKinX and CLKoutX or OSCout. On the other hand, if what you seek is actually a repeatable deterministic phase between power cycles, you must carefully select the PLL R and N divider values so that either the phase detector frequency of the PLLs is the GCD frequency of the input and output frequencies, or use the SYNC feature to reset the clock output phase at some precise time. Since OSCout does not have any synchronization feature, the only way to ensure repeatable deterministic phase on OSCout with respect to CLKout is to ensure that the PLL1 phase detector frequency is the GCD frequency of the input and the OSCout frequency. Given that every input and output frequency in the system is 80MHz, satisfying the GCD frequency constraint and establishing zero-delay is probably the easiest way to ensure deterministic phase on all outputs and OSCout with respect to CLKinX.

    In order to get CLKout and OSCout edges to align, you will likely need to adjust the CLKout digital and analog delay values and generate a SYNC pulse to adjust the CLKout delay to match OSCout (regardless of whether you use OSCin or PLL2 as the source).

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 20 points

    Hi Derek,

    thank you for your detailed answer.

    I am looking for repeatable deterministic phase between power cycles. Alignemt of the the edges is not needed. Since I can do a 80 MHz clock regemime I am fine.

    I myself wonder why TI removed the nested zero-delay dual loop mode as it is implented int he LMK0482x.

    Regards,
    HeHa

  • 0 in reply to HeHa
    TI__Mastermind 28960 points

    Hi HeHa,

    We redesigned the LMK0461x phase detectors to use a lower power architecture, but we discovered in validation that PLL1 phase detector does not track out wander very well at low loop bandwidths. We find that the absolute input-to-output phase of PLL1 wanders by ±2ns at <1Hz offsets, even at constant temperature, due to some underlying architecture effects. We did not want to offer a nested zero-delay dual loop mode if the input-to-output propagation delay variation was going to change by ±2ns. PLL2 does not have this issue, so the zero-delay mode remains available for PLL2.

    Regards,