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LMK04828: LMK04828 configuration

JH Shin
Mastermind 7105 points
Part Number: LMK04828

Hello,

My customer is using the LMK04828 in the system that uses the recovery clock received through an optical connection from the master unit as a reference clock.

In the system test, they found that the clock of the LMK04828 is not fixed and moves about 1 to 5Hz.

To resolve the issue, the customer do the following:

  -. When they change the PLL1_CP_GAIN from 50uA to 1550uA, the clock is fixed without movement. However, the phase noise of the clock is worse.

  -. When they double the value of the R&N counter of PLL1 the phase noise is improved.

Q1. When CP_GAIN is increased, is it correct that the frequency stability improves but phase noise worsens? Please explain why.

Q2. When the R&N counter in increased, is it correct that the clock phase noise improves? Please explain why.

Q3. Are there any other issues with the customer's final configuration?

The LMK04828 configuration file before the CP_GAIN and R/N counter change is attached.

LMK04828_BEFORE.tcs

Regards,

JH

  • 0
    TI__Expert 8585 points

    Hello JH,

    1.  This is correct. Typically when the CP_GAIN is increased it will widen the loop bandwidth which results in a worse noise behavior, but a more stable frequency.

    2. When the R and N divider are increased, the charge pump frequency decreases. The decrease in the charge pump results in a lower PLL phase noise, which results in the overall phase noise improvement.

    3. The changes you have made should be sufficient for fixing the frequency stability without significantly effecting the phase noise.

    Regards,

    Kia Rahbar