LMK04610: What is the minimal sysref request width required to generate sysref pulse?

Hi Dan,

The SYSREF request is re-timed by the VCO post-divider clock, so the request should be at least one post-divider clock cycle. In practice, I recommend that the pulse width is equal to one SYSREF period, to ensure that the pulse always finds a valid SYSREF edge.

The dividers used for SYSREF are continuously running during operation, and wait for a SYSREF_REQ signal to trigger a pulse at the rising edge of the divider's internal output. There should be a delay of six SYSREF cycles from the internal SYSREF divider rising edge to the generation of the output. In theory, if you can keep track of the SYSREF phase by monitoring an integer-related device clock, you should be able to generate a SYSREF_REQ pulse that will always trigger a SYSREF event at precisely the same latency. As long as the SYSREF internal edge timing can be predicted, and adequate setup time can be given to the SYSREF_REQ retimer so that at least one VCO post-divider clock cycle precedes the internal SYSREF divider edge, the SYSREF output latency should be reproducible.

Regards,