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LMK04828: MULTI-LMK04828 SPI ISSUE

Part Number: LMK04828

Hello team,

We're using 1 FPGA to driver 3 LMK04828 by 4-wire SPI, note that the CS pin is seperated but the other SPI pins are sharing line.

For the pin configuration, 0x149 is set to be 0x73.

The issue is that:

When we finish reading one LMK04828 register, MISO pin isn’t high-impedance status. Because.when there are more LMK04828 sharing the same line, the MISO voltage is lower, which caused the FPGA can’t read back registers normally. We are suspecting that the MISO pin isn't really high-impedance.

Is there an application suggestion for the multi-LMK case? Thank you.

Best Regards,

Qiang

  • Hi Qiang,

    My coworker will get back to you in a few hours.

    Regards,
    Hao

  • Hello Qiang,

    Do you have a schematic showing how they have connected the SPI interface?

    It sounds like they are using CLKin_SEL1 on all devices as the shared MISO in a 4-wire configuration (please confirm?) but 0x149 set to 0x73 sets CLKin_SEL1 to push-pull output type. SDIO_RDBK_TYPE only applies to the SDIO pin. If they want an alternate output such as CLKin_SEL1 to be high impedance, they must set the output format to open drain e.g. 0x149=0x76 and use an external pull-up resistor.

    Regards,