Hello team,
We're using 1 FPGA to driver 3 LMK04828 by 4-wire SPI, note that the CS pin is seperated but the other SPI pins are sharing line.
For the pin configuration, 0x149 is set to be 0x73.
The issue is that:
When we finish reading one LMK04828 register, MISO pin isn’t high-impedance status. Because.when there are more LMK04828 sharing the same line, the MISO voltage is lower, which caused the FPGA can’t read back registers normally. We are suspecting that the MISO pin isn't really high-impedance.
Is there an application suggestion for the multi-LMK case? Thank you.
Best Regards,
Qiang