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LMK05028EVM: TIICSPRO .tcs data

Hirotaka Matsumoto
Guru 27525 points
Part Number: LMK05028EVM
Other Parts Discussed in Thread: LMK05028, LMH1981

Hi all

Would you mind if we ask LMK05028EVM?

Our customer tries to configure following system using LMH1981 and LMK05028.




In case video format NTSC 525i, they would like to configure OUT0 = OUT1 = 148.5e6/1.001.  
In case video format PAL 625i, they would like to configure OUT0 = OUT1 = 148.5e6.  

If you have some above TICSPRO's .tcs file using LMK05028EVM, could you share us?

Kind regards,

Hirotaka Matsumoto

  • 0
    TI__Expert 6140 points

    Hello,

    You can use the main:start page on TICSpro and step through steps 1 - 6, runscript, and generated the needed configuration.

    From the above, I only see one input on LMK05028. LMK05028 requires an XO + a reference input if DPLL functionality is needed.

    Thanks and regards,

    Amin

  • 0 in reply to Amin Eshraghi
    Guru 27525 points

    Amin san

    Thank you so much for your reply.

    We attaches the .tcs files.
    20210318_LMK05028EVM_525_HSYNC.TCS20210318_LMK05028EVM_625_HSYNC.TCS

    <Question1>
    How much of the input reference jitter does the device allow?
    Because, we guess that the Hsync contains jitter.

    <Question2>
    How much is pull in range for Lock?
    We would like to confirm DPLL's pull in range.

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Expert 6140 points

    Hi Hirotaka - san,

    Question1: The reference inputs has a number of validation settings including missing clock, ppm detector, amplitude detector among others to validate / invalidate the input. There isn't any specific jitter spec. We've been able to lock with really high phase jitter (3 - 5 picoseconds) on the reference input but this isn't a characterized parameter so not sure about robustness.

    Question 2: This is also another item that's not necessarily specified but it will depend on what the reference is doing. As long as the reference remains valid the DPLL will lock and follow the reference. The validity of the reference will depend on how many validation detectors are enabled and how strict the settings are. If ppm level of accuracy isn't needed, that detector can be turned off. Missing clock is good to enable for when clock is completely lost - DPLL would then enter holdover - maintain frequency set by the XO (free - run).

    Thanks and regards,

    Amin

  • 0 in reply to Amin Eshraghi
    Guru 27525 points

    Amin san

    Thank you so much for your reply!

    Can you let me know some more details of lock detection circuit of the DPLL?
    How does the DPLL determine the LOCK of the DPLL?
    We suppose the LOCK detection circuit in the DPLL compares the phase difference between the divided VCO clock and divided reference clock.

    If so, can you let m know the tolerance of the phase difference to maintain he LOCK by design?

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Expert 6140 points

    Hi Hirotaka - san,

    Yes, that is correct in terms of how the lock detection is designed. Once a runscript is run, these detectors get set per your configuration inputs - reference frequency, TDC rate, VCO frequency, etc. You can manually adjust these detector to loosen or tighten the setting but it's generally not recommended. You can see these detectors tolerance under the DPLL Phase Lock Detectors sections on the Main: start page tab.

    Thanks and regards,

    Amin

  • 0 in reply to Amin Eshraghi
    Guru 27525 points

    Amin san

    Thank you so much for your cooperation always!

    You can manually adjust these detector to loosen or tighten the setting but it's generally not recommended.
    ->Could you let us know why manual adjustment is not recommended? 
       Because, using this device, we assume that it is merit to remove the large jitter.

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Expert 6140 points

    Hi Hirotaka -san,

    The question is what is the end purpose. You can increase it as much as you want and have it tell you it's locked flag wise, but device may not be behaving in a lock manner - 0 ppm vs reference, following the reference, DCO, etc. I wouldn't assume that the lock threshold needs to be increased in order to achieve lock because again while it may flag it as lock it may not behave as it is locked.

    I recommend test in system with the reference from LMH1981 connected and see whether it validate the reference or not. If it does, then it should be able to stay locked to it.

    Thanks and regards,

    Amin

  • 0 in reply to Amin Eshraghi
    Guru 27525 points

    Amin san

    Thank you so much for your reply!
    OK, we got your mention.

    On the other hand, if you have some detail document of video clock using LMK05028+LMH1981, could you share us it?
    www.ti.com/.../snaa314

    The is no detail description for TICSPRO's setting.

    Kind regards,

    Hirotaka Matsumoto

  • +1 in reply to Hirotaka Matsumoto
    TI__Expert 6140 points

    Hi Hirotaka -san,

    I'm not aware of any LMK05028 + LMH1981 usage. Typically audio/video system doesn't need a DPLL functionality from what I know usually a DPLL device isn't used. Is that something that's necessary for your system?

    Best recommendation for using TICSpro is to start with the main: start page and just step through steps 1 - 6, runscript to generate configuration.

    Thanks and regards,

    Amin