LMK05318BEVM: Crystal oscillators and phase noise relationship

Part Number: LMK05318BEVM
Other Parts Discussed in Thread: PLLATINUMSIM-SW

Hi E2E,

Good day.

Our customer is using the LMK05318BEVM and they have change the 48.0048-MHz onboard crystal oscillator to 32.768 MHz and observed degradation of about 10dB in phase noise. How the crystal frequency affects phase noise? What are the requirements on the crystal oscillators so that phase noise is not degraded? Their application requires low phase noise 100MHz and 140MHz signals and they need to vary the crystal oscillators between 12 to 48 MHz without phase noise degradation.


Regards,
Carlo

  • Hello Carlo,

    At what offset is the degradation?

    The XO will impact noise below the analog PLL loop bandwidth.  Low phase detector frequency will increase the PLL in-band noise, however I would not expect a 10 dB loss.

    Can you share a before/after phase noise plot?  Can you share a plot of the 32.768 MHz XO?

    I expect the 100 MHz is coming from APLL1 and 140 MHz from APLL2.

    Have you tried using the PLLatinum Sim tool (www.ti.com/.../PLLATINUMSIM-SW) It is possible to load the XO phase noise and simulate the expected results.

    73,
    Timothy

  • Hello Timothy,

    According to our customer, the degradation in phase noise was at an offset of 10kHz. Unfortunately, their setup has been taken apart and there are no plots available. If there will be any additional details from the customer, I will share them with you.


    Regards,
    Carlo

  • Hi Timothy,

    Good day.

    Please refer to the attached file for the testing conducted by our customer. The two configuration files are also provided in .txt file and you can change the extension back to.tcs. Based on the result, the customer is not getting a BAW lock.

    LMK05318BEVM Phase Noise Problem with 32.768MHz oscillator.doc

    210506 LMK0518EVM 32.768MHz Osc 10MHz Ref.txt
    [SETUP]
    ADDRESS=888
    CLOCK=8
    DATA=4
    LE=2
    PART=LMK05318B
    IFACE=I2C
    ADDRESS_I2C=0x65
    INTERFACE_SPEED=400
    
    [PINS]
    PINNAME00=REFSEL
    LOCATION00=9
    PINVALUE00=False
    PINNAME01=HW_CTRL
    LOCATION01=7
    PINVALUE01=False
    PINNAME02=PDN
    LOCATION02=3
    PINVALUE02=True
    PINNAME03=GPIO0
    LOCATION03=8
    PINVALUE03=False
    PINNAME04=GPIO1
    LOCATION04=6
    PINVALUE04=False
    PINNAME05=GPIO2
    LOCATION05=5
    PINVALUE05=False
    PINNAME06=Status0
    LOCATION06=10
    PINVALUE06=False
    PINNAME07=Status1
    LOCATION07=11
    PINVALUE07=False
    
    [MODES]
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    [FLEX]
    CH0_PREDRIVER=0
    CH1_PREDRIVER=0
    CH2_PREDRIVER=0
    CH3_PREDRIVER=0
    CH4_PREDRIVER=0
    CH5_PREDRIVER=0
    CH6_PREDRIVER=0
    CH7_PREDRIVER=0
    DPLL_REF_LOOPCTL_CHG_QUANT_INTG=0
    DPLL_REF_MASHSEED=0
    DPLL_REF_UNLOCKDET_CNTSTRT=0
    DPLL_REF_UNLOCKDET_VCO_CNTSTRT=0
    MUTE_DPLL_FRLOCK=1
    OUT0_freq=140.0 MHz
    OUT1_freq=140.0 MHz
    OUT2_freq=140.0 MHz
    OUT3_freq=140.0 MHz
    OUT4_freq=100.0 MHz
    OUT5_freq=100.0 MHz
    OUT6_freq=100.0 MHz
    OUT7_freq=100.0 MHz
    PLL1_BAW_CAPDAC=0
    PLL1_CP_TRIM=0
    PLL1_VCBO_VAR2CON=0
    PRIREFBUFGAIN=0
    SECREFBUFGAIN=0
    VCO1_freq=2500
    VCO2_freq=6160
    XO_freq=32.768
    bFindAddressBtn=Find I2C Addr
    i2cAddr=0
    sTDC_freq=10.0 MHz
    btn_page0_next=NEXT>
    combo_backward_compatible=0
    combo_dpll_mode=0
    combo_ref_freq=1
    matlab_runtime_url=https://www.mathworks.com/products/compiler/matlab-runtime.html
    btn_page1_back=<BACK
    btn_page1_next=NEXT>
    btn_xo_show_instructions=Show Instructions
    sXO_freq=32768000
    s_wizard_XO_message_box=INSTRUCTIONS:\n\n1. Set XO frequency in Hz. Example frequency formats:\n\n48e6\n100e6 / 3\n48e6 * (1 + 100e-6)\n\nIf DPLL is disabled, then XO frequency can be 25 MHz or 50 MHz for APLL1 to work in integer mode.\n\nIf DPLL is enabled then recommended XO frequencies are 12.8 MHz, 19.2 MHz, 24 MHz, 30.72 MHz, 38.88 MHz, 48 MHz and 48.0048 MHz. For 1-pps reference input, low frequency and high stability XO is recommended. For example, 12.8 MHz TCXO or OCXO.\n\n2. The XO doubler and R divider are automatically set. To manually set the R divider and XO doubler, go to tab 'Advanced' -> 'APLL1'. If the DPLL is disabled, then there's no restriction on PFD frequency, as long as it's within the PFD frequency range (10.0 MHz to 100.0 MHz). If the DPLL is enabled, however, two conditions must be met:\n\n(1) The fractional part of BAW VCO frequency (2.5 GHz) divided by PFD frequency must be within 0.0625 and 0.9375.\n\n(2) The minimum difference between BAW VCO frequency (2.5 GHz) and any multiple of PFD frequency must be beyond 2.5 GHz * 1000 ppm.\n\nThe wizard selects the highest PFD frequency that meets both requirements.\n\n3. Select the XO interface type according to the selection tips.
    OUT0_freq=140.0 MHz
    OUT1_freq=140.0 MHz
    OUT2_freq=140.0 MHz
    OUT3_freq=140.0 MHz
    OUT4_freq=100.0 MHz
    OUT5_freq=100.0 MHz
    OUT6_freq=100.0 MHz
    OUT7_freq=100.0 MHz
    PLL1_RDIV_StaticText=PLL2 R divider (two stages)
    bCALC_FREQPLAN=Calculate Frequency Plan
    btn_freq_plan_show_instructions=Show Instructions
    btn_frequency_plan_apply_solution=Apply selected solution
    btn_page2_back=<BACK
    btn_page2_next=NEXT>
    cb_allow_PLL2_prescaler_of_2=0
    cb_manual_override_pll2_rdiv=0
    sCH0_1_IN_freq=140000000
    sCH0_1_MUX=APLL2
    sCH2_3_IN_freq=140000000
    sCH2_3_MUX=APLL2
    sCH4_IN_freq=100000000
    sCH4_MUX=APLL1
    sCH5_IN_freq=100000000
    sCH5_MUX=APLL1
    sCH6_IN_freq=100000000
    sCH6_MUX=APLL1
    sCH7_IN_freq=100000000
    sCH7_MUX=APLL1
    s_wizard_freqplan_message_box=Frequency plan completed!\n\nSelected frequency plan:\n\nVCO1 frequency = 2500.0 MHz\nVCO2 frequency = 6160.0 MHz\n\nAPLL1 settings:\n\nPFD freq = 65536000 Hz\nN divider = 38\nNumerator = 161598144512\nDenominator = 1099511627776\nPost divider = 1\n\nAPLL2 settings:\n\nAPLL2 reference source is VCO1\nPFD freq = 1250000000/9 Hz\nN divider = 44\nNumerator = 4400\nDenominator = 12500\nPost divider 1 = 4\nPost divider 2 = 4\n\n
    table_frequency_plan_pll1=0
    table_frequency_plan_pll2=0
    btn_page3_back=<BACK
    btn_page3_next=NEXT>
    btn_refclk_show_instructions=Show Instructions
    cb_enable_PRIREF=1
    cb_enable_SECREF=0
    combo_PRIREF_BUF_TYPE=1
    combo_SECREF_BUF_TYPE=1
    combo_ref_priority=0
    refclk_pin_select=
    sPRIREF_freq=10000000
    sSECREF_freq=
    s_wizard_refclk_message_box=INSTRUCTIONS:\n\n1. Enable or disable PRIREF and SECREF as needed. If DPLL is not used, then disable both references and skip this page.\n\n2. Type the frequencies of PRIREF and / or SECREF in Hz. Example frequency formats:\n\n1\n25e6\n100e6 / 3\n\n3. Select interface type. AC or DC buffer is auto-seletected based on reference frequency. If reference frequency is below 5 MHz, then use DC buffer. Otherwise, use AC buffer. To select interface types for AC buffer, refer to the 'Interface Type Selection Tips' in the XO wizard page. The same can be applied to PRIREF and SECREF.\n\n4. Select the input switching mode. The input switching mode is auto-seletected based on the states of PRIREF and SECREF enable. When both references are enabled, then Auto non-revertive is selected. If only one reference is enabled, then manual holdover is selected. However, it is highly recommended to read through the 'Input Switching Mode Selection Guide' in this wizard page and make the decision.\n\n5. If manual fallback or manual holdover is selected, then choose between manually select by register and manually select by REFSEL pin.
    btn_page4_back=<BACK
    btn_page4_next=NEXT>
    btn_ref_validation_show_instructions=Show Instructions
    sPRIREF_ACCURACY_PPM=10
    sPRIREF_AVG_COUNT=2
    sPRIREF_EARLY_MARGIN=1
    sPRIREF_EARLY_calc=7.20 ns
    sPRIREF_LATE=0
    sPRIREF_LATE_MARGIN=1
    sPRIREF_LATE_calc=5.60 ns
    sPRIREF_PH_VALID_calc=n/a
    sPRIREF_PPM_INVALID=110
    sPRIREF_PPM_TIMER=3.05 ms
    sPRIREF_PPM_VALID=100
    sSECREF_ACCURACY_PPM=10
    sSECREF_AVG_COUNT=2
    sSECREF_EARLY_MARGIN=1
    sSECREF_EARLY_calc=n/a
    sSECREF_LATE=0
    sSECREF_LATE_MARGIN=1
    sSECREF_LATE_calc=n/a
    sSECREF_PH_VALID_calc=n/a
    sSECREF_PPM_INVALID=110
    sSECREF_PPM_TIMER=n/a
    sSECREF_PPM_VALID=100
    s_wizard_reference_validation_message_box=INSTRUCTIONS:\n\nIf DPLL is disabled, then skip this page. All reference validation methods have been enabled or disabled automatically based on reference frequency and interface type. However, it is highly recommended to read through the instructions and loose or tighten the thresholds according to application needs.\n\nFrequency detection and early / late window detection are only valid for reference frequencies >= 2 kHz. 1-pps phase detector is only valid for reference frequencies < 2 kHz. For 1-pps input, only enable the 1-pps phase detector and disable all other detectors.\n\n1. Validation timer. The reference must stay valid for 'validation timer' amount of time before it's considered valid. It is recommended to set the validation timer to more than twice of the total reference validation measurement time. The frequency detection measurement time is displayed on the wizard. Measurement time of amplitude detection, early / late clock detection as well as 1-pps phase detection is roughly one cycle of reference clock. Therefore, if the reference frequency is >= 2 kHz, total measurement time is approximately the frequency detection measurement time. If the reference frequency is < 2 kHz, total measuremnet time is approximately 1 cycle of reference clock.\n\n2. Amplitude detector. There are two modes: amplitude detector mode and CMOS slew rate detector mode. In amplitude detector mode, the reference is considered valid if the signal swing is higher than the selected threshold. In CMOS slew rate detector mode, the detection method can be either slew rate detection or VIH / VIL detection. For slew rate detection, the input slew rate must be faster than 0.2 V/ns. For VIH / VIL detection, the input high level must be above 1.8 V and the low level must be below 0.6 V. The amplitude detection mode cannot be used for reference frequencies less than 5 MHz. If the reference frequency is above 5 MHz, then amplitude detection mode is recommended for differential input and the CMOS slew rate detection mode is recommended for single-ended input. If the input swing is too low (for example, the LVDS voltage swing is 400 mV, very marginal compared to the mininum threshold of amplitude detection mode), then amplitude detector can be disabled.\n\n3. Frequency detector. This detector is only valid for PRIREF / SECREF frequencies >= 2 kHz. Frequency detection needs 4 parameters: valid threshold in ppm, invalid threshold in ppm, accuracy in ppm and average count. The PRIREF or SECREF is considered valid if the frequency error between PRIREF / SECREF and XO is within the valid threshold. While it's frequency valid, it's considered as frequency invalid if the frequency error exceeds the invalid threshold. The accuracy in ppm indicates how accurate the valid and invalid threshold can be. In other words, this is the resolution of valid and invalid threshold counters. The minimum average count is 2. Keep it as 2 unless the reference clock has too much wander and the DPLL loop bandwidth is too narrow. In that case, raise the average count to no more than 10. As mentioned, the '0-error' reference for frequency detection is the XO. In reality, of course, the XO frequency is not '0-error'. Therefore, the valid and invalid thresholds must take the XO ppm error into account. The minimum valid threshold should be max XO frequency error + max PRIREF / SECREF frequency error + accuracy in ppm. The minimum invalid threshold should be valid threshold + accuracy in ppm.\n\n4. Early and late clock window detector. This detector is only valid for PRIREF / SECREF frequencies >= 2 kHz. 3 parameters are needed: early counter, late counter and number of missing clocks. After setting early and late counters, the T_early and T_late are calculated accordingly. As shown in the timing diagram, the PRIREF / SECREF is considered valid if its next clock edge falls within ideal next edge - T_early and ideal next edge + T_late. Setting the number of missing clocks to x is equivalent to adding x * reference_clock_period to T_late. So the number of missing clocks is typically set to 0 unless gapped clock needs to be supported. The early and late clock detector uses divided down BAW VCO frequency as its '0-error' reference. However, since this is a very coarse detection method (resolution of T_early and T_late counter is roughly 1.6 ns), the ppm error of the BAW VCO itself is not of concern.\n\n5. 1-pps phase detector. This detector is only valid for PRIREF / SECREF frequencies < 2 kHz. T_jitter is auto-calculated according to the phase detector counter. As shown in the timing diagram, the PRIREF / SECREF is considered valid if the next clock edge falls within ideal next edge - T_jitter and ideal next edge + T_jitter. Note that the '0-error' clock reference for 1-pps phase detector is the XO, so T_jitter must be greater than the sum of: (1) XO phase error accumulated through one PRIREF / SECREF clock period (for example, 1 second for 1-pps input). This includes the phase error caused by frequency inaccuracy, accumulated jitter as well as wander. (2) The max period jitter of PRIREF / SECREF. Therefore, low frequency and high stability XO is recommended for 1-pps input. This is because for XOs with the same frequency stability, the one with the lower frequency accumulates less phase error over fixed period of time. 12.8 MHz TCXO / OCXO is recommended for 1-pps input.
    DPLL_VCO_freq=2500
    bRUN_SCRIPT=Run Script
    btn_dpll_show_instructions=Show Instructions
    btn_page5_back=<BACK
    btn_page5_next=NEXT>
    btn_restore_dpll_reg=Restore Calculated DPLL Settings
    cb_show_dpll_registers=0
    combo_disable_fastlock=0
    combo_set_max_tdc_freq=0
    combo_switching_method=0
    sDPLL_LBW=100
    sDPLL_LBW_ACT=101.4
    sDPLL_PEAK=0.1
    sDPLL_PEAK_ERROR=1
    sMAX_TDC_freq=26000000
    sPRIREF_freq_display=10.0 MHz
    sSECREF_freq_display=Disabled
    sTDC_freq=10.0 MHz
    s_wizard_dpll_message_box=DPLL calculation completed!\n\nTDC frequency = 10000000\n\nPlanned VCO1 frequency = 2500000000\nActual VCO1 frequency = 2500000000\nPLL1 frequency error = 0 ppb\n\nPlanned VCO2 frequency = 6160000000\nActual VCO2 frequency = 6160000000\nPLL2 frequency error = 0 ppb\n\nDPLL fastlock time = 124.52 ms + 12.70 ms = 137.22 ms\n\nTotal DPLL frequency lock time ~= DPLL fastlock time + 2 * DPLL frequency lock measurement time\n\nTotal DPLL phase lock time ~= DPLL fastlock time + 2 * DPLL phase lock measurement time
    BAW_LOCK_PPM_THRESH=5
    BAW_UNLK_PPM_THRESH=10
    DPLL_PL_LOCK_calc=377.86 ps
    DPLL_PL_UNLK_calc=6.05 ns
    btn_baw_lock_detect_default=Set Default
    btn_dpll2_show_instructions=Show Instructions
    btn_dpll_freq_lock_detect_default=Set Default
    btn_history_recommend=Min Values Required
    btn_page6_back=<BACK
    btn_page6_next=NEXT>
    btn_ph_threshold_recommend=Recommended
    sBAW_LOCK_ACCURACY_PPM=1
    sBAW_LOCK_AVG=2
    sBAW_TMEAS_LOCK_calc=19.2000 ms
    sDPLL_HISTCNT_calc=26.21 ms
    sDPLL_HISTDLY_calc=24.58 ms
    sDPLL_LOCK_ACCURACY_PPM=1
    sDPLL_LOCK_AVG=10
    sDPLL_LOCK_PPM=1
    sDPLL_PL_MEAS_TIME=9.86 ms
    sDPLL_TMEAS_LOCK_calc=96.0000 ms
    sDPLL_UNLK_PPM=10
    s_wizard_dpll2_message_box=INSTRUCTIONS:\n\nAll lock detect settings are set to either default or recommended values after the DPLL script is run. Still, it is highly recommended to go through the instructions and make the adjustments.\n\n1. BAW frequency lock detect. Disable this if DPLL is enabled. This detector is only useful if the DPLL is disabled and the device works in free-running mode. Enter lock threshold in ppm, unlock threshold in ppm, average count (min value = 2) and accuracy in ppm. The BAW (VCO1) is considered to be locked if the frequency error between the BAW and the XO is within lock threshold. Once the BAW is locked, it's considered to be unlocked if the frequency error exceeds the unlock threshold. The step size of lock and unlock threshold in ppm = accuracy / average. If there's no specific requirement for BAW lock detect, click 'Set Default'.\n\n2. DPLL frequency lock detect. Enter lock and unlock thresholds in ppm, average count (min value = 2) as well as accuracy in ppm. The DPLL is considered to be frequency locked if the frequency error between the VCO1 and the references is within the lock threshold. While the DPLL is frequency locked, it's considered to be frequency unlocked if the frequency error exceeds the unlock threshold. The step size of lock and unlock threshold =  accuracy / average. If there's no specific requirement for DPLL frequency lock detect, click 'Set Default'.\n\n3. DPLL phase lock detect. Set lock and unlock threshold counters. The actual lock and unlock thresholds in second are then calculated accordingly. The DPLL is considered as phase locked if the phase difference between the two inputs of TDC (divided reference and divided VCO1) is within the lock threshold. While the DPLL is phase locked, it's considered as phase unlocked if the phase difference exceeds the unlock threshold. Use recommended values for this. The lock and unlock counters should not be manually set, and they are only used for engineering debugging purposes.\n\n4. Tuning word history. This block sets the tuning word history for holdover. Set history counter and delay counter. The averaging time and delay time are then auto-calculated. Refer to datasheet section '9.3.7.4 Tuning Word History' for details. If there's no specific requirement for holdover tuning word, click 'Min Values Required'. This makes sure that the delay time is more than 8 times of the reference frequency validation measurement time, and that the averaging time is longer than the delay time.
    btn_page7_back=<BACK
    PLL1_24b_DEN=0
    PLL1_24b_NUM=9632
    PLL1_DEN=1099511627776
    PLL1_PFD_freq=65.536
    VCO1_freq=2500
    XO_freq=32.768
    PLL2_DEN_fixed=16777216
    PLL2_PFD_freq=138.8888888889
    VCO1_freq=2500
    VCO2_freq=6160
    XO_freq=32.768
    MUTE_DPLL_FRLOCK=1
    OUT0_freq=140.0 MHz
    OUT1_freq=140.0 MHz
    OUT2_freq=140.0 MHz
    OUT3_freq=140.0 MHz
    OUT4_freq=100.0 MHz
    OUT5_freq=100.0 MHz
    OUT6_freq=100.0 MHz
    OUT7_freq=100.0 MHz
    PLL2PDIV1_freq=1540
    PLL2PDIV2_freq=1540
    VCO1_freq=2500
    VCO2_freq=6160
    sOUT7_DIV=25
    AbsDCO_ppb_error=0.01
    DPLL_DCO_FREQ_PPB_ACT=0
    DPLL_DCO_STEP_ACT=0
    DPLL_REF_NUM_calculated=549755813888
    bDPLL_FDECR=Decrement
    bDPLL_FINCR=Increment
    bResetNumerator0ppb=Reload Original DPLL Numerator
    cbDCO_MODE=1
    sDPLL_DCO_STEP=0.01
    sSYNC_PHASE_OFFSET=
    bClearAllFlagStickyStatus=Clear All Flags
    bReadStatus=Read Status
    ADDR_10=200
    ADDR_11=0
    ADDR_249=0
    ADDR_250=0
    ADDR_251=0
    ADDR_252=0
    REGCOMMIT_PG=0
    bEXPORTEEPROMFILE=Export GUI Map --> EEPROM File
    bIMPORTEEPROMFILE=(1b) Import EEPROM File --> GUI Map
    bLoadDefaultEEPROMImageToGUIMap=(1c) Load Default EEPROM Image --> GUI Map
    bLoadPage_from_GUIMap_to_GUI_Registers=Load GUI Map PAGE --> Register
    bPROGRAMEEPROM=(3) Program EEPROM <-- SRAM
    bREADBACKEEPROM=Read All EEPROM --> GUI Map
    bREADBACKROM=Read All ROM --> GUI Map
    bREADBACKSRAM=Read All SRAM --> GUI Map
    bREG2EE=(1a) Commit Registers --> SRAM PAGE/GUI Map
    bUpdate_ExtraEEPROM_Bytes=Read Extra\nEEPROM Bytes
    cbEESLAVEADR=0
    cbWrite_ADR10=0
    cbWrite_ADR11=0
    mtc_EEPROMdump=
    mtc_USERNOTES=Enter User Notes
    tc_DESIGNNAME=Enter Design Name
    bButton1=Builtins
    bButton2=Globals
    bButton3=Button 3
    bButton4=ReLoad Scripts
    bButton5=Button 5
    bClear=Clear
    bEnter=Enter
    bLoadButton=Load Script
    bSetButton=Set Script
    bSystemUpdate=SystemUpdate
    bSystemUpdateRunOnce=SystemUpdateRunOnce
    cbButtonSelect=0
    mtcOutput=UpdateStatusBar("Hello World")
    mtcScript=0
    tcInput=UpdateStatusBar("Goodbye World")
    tcLHS=0
    
    210506 LMK0518EVM 48.0048MHz Osc 10MHz Ref.txt
    [SETUP]
    ADDRESS=888
    CLOCK=8
    DATA=4
    LE=2
    PART=LMK05318B
    IFACE=I2C
    ADDRESS_I2C=0x65
    INTERFACE_SPEED=400
    
    [PINS]
    PINNAME00=REFSEL
    LOCATION00=9
    PINVALUE00=False
    PINNAME01=HW_CTRL
    LOCATION01=7
    PINVALUE01=False
    PINNAME02=PDN
    LOCATION02=3
    PINVALUE02=True
    PINNAME03=GPIO0
    LOCATION03=8
    PINVALUE03=False
    PINNAME04=GPIO1
    LOCATION04=6
    PINVALUE04=False
    PINNAME05=GPIO2
    LOCATION05=5
    PINVALUE05=False
    PINNAME06=Status0
    LOCATION06=10
    PINVALUE06=False
    PINNAME07=Status1
    LOCATION07=11
    PINVALUE07=False
    
    [MODES]
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    VALUE00=16
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    [FLEX]
    CH0_PREDRIVER=0
    CH1_PREDRIVER=0
    CH2_PREDRIVER=0
    CH3_PREDRIVER=0
    CH4_PREDRIVER=0
    CH5_PREDRIVER=0
    CH6_PREDRIVER=0
    CH7_PREDRIVER=0
    DPLL_REF_LOOPCTL_CHG_QUANT_INTG=0
    DPLL_REF_MASHSEED=0
    DPLL_REF_UNLOCKDET_CNTSTRT=0
    DPLL_REF_UNLOCKDET_VCO_CNTSTRT=0
    MUTE_DPLL_FRLOCK=1
    OUT0_freq=140.0 MHz
    OUT1_freq=140.0 MHz
    OUT2_freq=140.0 MHz
    OUT3_freq=140.0 MHz
    OUT4_freq=100.0 MHz
    OUT5_freq=100.0 MHz
    OUT6_freq=100.0 MHz
    OUT7_freq=100.0 MHz
    PLL1_BAW_CAPDAC=0
    PLL1_CP_TRIM=0
    PLL1_VCBO_VAR2CON=0
    PRIREFBUFGAIN=0
    SECREFBUFGAIN=0
    VCO1_freq=2500
    VCO2_freq=6160
    XO_freq=48.0048
    bFindAddressBtn=Find I2C Addr
    i2cAddr=0
    sTDC_freq=10.0 MHz
    btn_page0_next=NEXT>
    combo_backward_compatible=0
    combo_dpll_mode=0
    combo_ref_freq=1
    matlab_runtime_url=https://www.mathworks.com/products/compiler/matlab-runtime.html
    btn_page1_back=<BACK
    btn_page1_next=NEXT>
    btn_xo_show_instructions=Show Instructions
    sXO_freq=48004800
    s_wizard_XO_message_box=XO frequency set successfully!\n\nInteger boundary spur = 3.75 MHz\n\nXO R divider = 1\nXO doubler is disabled\nPFD frequency = 48.0048 MHz
    OUT0_freq=140.0 MHz
    OUT1_freq=140.0 MHz
    OUT2_freq=140.0 MHz
    OUT3_freq=140.0 MHz
    OUT4_freq=100.0 MHz
    OUT5_freq=100.0 MHz
    OUT6_freq=100.0 MHz
    OUT7_freq=100.0 MHz
    PLL1_RDIV_StaticText=PLL2 R divider (two stages)
    bCALC_FREQPLAN=Calculate Frequency Plan
    btn_freq_plan_show_instructions=Show Instructions
    btn_frequency_plan_apply_solution=Apply selected solution
    btn_page2_back=<BACK
    btn_page2_next=NEXT>
    cb_allow_PLL2_prescaler_of_2=0
    cb_manual_override_pll2_rdiv=0
    sCH0_1_IN_freq=140000000
    sCH0_1_MUX=APLL2
    sCH2_3_IN_freq=140000000
    sCH2_3_MUX=APLL2
    sCH4_IN_freq=100000000
    sCH4_MUX=APLL1
    sCH5_IN_freq=100000000
    sCH5_MUX=APLL1
    sCH6_IN_freq=100000000
    sCH6_MUX=APLL1
    sCH7_IN_freq=100000000
    sCH7_MUX=APLL1
    s_wizard_freqplan_message_box=Frequency plan completed!\n\nSelected frequency plan:\n\nVCO1 frequency = 2500.0 MHz\nVCO2 frequency = 6160.0 MHz\n\nAPLL1 settings:\n\nPFD freq = 48004800 Hz\nN divider = 52\nNumerator = 85899918525\nDenominator = 1099511627776\nPost divider = 1\n\nAPLL2 settings:\n\nAPLL2 reference source is VCO1\nPFD freq = 1250000000/9 Hz\nN divider = 44\nNumerator = 4400\nDenominator = 12500\nPost divider 1 = 4\nPost divider 2 = 4\n\n
    table_frequency_plan_pll1=0
    table_frequency_plan_pll2=0
    btn_page3_back=<BACK
    btn_page3_next=NEXT>
    btn_refclk_show_instructions=Show Instructions
    cb_enable_PRIREF=1
    cb_enable_SECREF=0
    combo_PRIREF_BUF_TYPE=1
    combo_SECREF_BUF_TYPE=1
    combo_ref_priority=0
    refclk_pin_select=
    sPRIREF_freq=10000000
    sSECREF_freq=
    s_wizard_refclk_message_box=INSTRUCTIONS:\n\n1. Enable or disable PRIREF and SECREF as needed. If DPLL is not used, then disable both references and skip this page.\n\n2. Type the frequencies of PRIREF and / or SECREF in Hz. Example frequency formats:\n\n1\n25e6\n100e6 / 3\n\n3. Select interface type. AC or DC buffer is auto-seletected based on reference frequency. If reference frequency is below 5 MHz, then use DC buffer. Otherwise, use AC buffer. To select interface types for AC buffer, refer to the 'Interface Type Selection Tips' in the XO wizard page. The same can be applied to PRIREF and SECREF.\n\n4. Select the input switching mode. The input switching mode is auto-seletected based on the states of PRIREF and SECREF enable. When both references are enabled, then Auto non-revertive is selected. If only one reference is enabled, then manual holdover is selected. However, it is highly recommended to read through the 'Input Switching Mode Selection Guide' in this wizard page and make the decision.\n\n5. If manual fallback or manual holdover is selected, then choose between manually select by register and manually select by REFSEL pin.
    btn_page4_back=<BACK
    btn_page4_next=NEXT>
    btn_ref_validation_show_instructions=Show Instructions
    sPRIREF_ACCURACY_PPM=10
    sPRIREF_AVG_COUNT=2
    sPRIREF_EARLY_MARGIN=1
    sPRIREF_EARLY_calc=7.20 ns
    sPRIREF_LATE=0
    sPRIREF_LATE_MARGIN=1
    sPRIREF_LATE_calc=5.60 ns
    sPRIREF_PH_VALID_calc=n/a
    sPRIREF_PPM_INVALID=110
    sPRIREF_PPM_TIMER=4.17 ms
    sPRIREF_PPM_VALID=100
    sSECREF_ACCURACY_PPM=10
    sSECREF_AVG_COUNT=2
    sSECREF_EARLY_MARGIN=1
    sSECREF_EARLY_calc=n/a
    sSECREF_LATE=0
    sSECREF_LATE_MARGIN=1
    sSECREF_LATE_calc=n/a
    sSECREF_PH_VALID_calc=n/a
    sSECREF_PPM_INVALID=110
    sSECREF_PPM_TIMER=n/a
    sSECREF_PPM_VALID=100
    s_wizard_reference_validation_message_box=INSTRUCTIONS:\n\nIf DPLL is disabled, then skip this page. All reference validation methods have been enabled or disabled automatically based on reference frequency and interface type. However, it is highly recommended to read through the instructions and loose or tighten the thresholds according to application needs.\n\nFrequency detection and early / late window detection are only valid for reference frequencies >= 2 kHz. 1-pps phase detector is only valid for reference frequencies < 2 kHz. For 1-pps input, only enable the 1-pps phase detector and disable all other detectors.\n\n1. Validation timer. The reference must stay valid for 'validation timer' amount of time before it's considered valid. It is recommended to set the validation timer to more than twice of the total reference validation measurement time. The frequency detection measurement time is displayed on the wizard. Measurement time of amplitude detection, early / late clock detection as well as 1-pps phase detection is roughly one cycle of reference clock. Therefore, if the reference frequency is >= 2 kHz, total measurement time is approximately the frequency detection measurement time. If the reference frequency is < 2 kHz, total measuremnet time is approximately 1 cycle of reference clock.\n\n2. Amplitude detector. There are two modes: amplitude detector mode and CMOS slew rate detector mode. In amplitude detector mode, the reference is considered valid if the signal swing is higher than the selected threshold. In CMOS slew rate detector mode, the detection method can be either slew rate detection or VIH / VIL detection. For slew rate detection, the input slew rate must be faster than 0.2 V/ns. For VIH / VIL detection, the input high level must be above 1.8 V and the low level must be below 0.6 V. The amplitude detection mode cannot be used for reference frequencies less than 5 MHz. If the reference frequency is above 5 MHz, then amplitude detection mode is recommended for differential input and the CMOS slew rate detection mode is recommended for single-ended input. If the input swing is too low (for example, the LVDS voltage swing is 400 mV, very marginal compared to the mininum threshold of amplitude detection mode), then amplitude detector can be disabled.\n\n3. Frequency detector. This detector is only valid for PRIREF / SECREF frequencies >= 2 kHz. Frequency detection needs 4 parameters: valid threshold in ppm, invalid threshold in ppm, accuracy in ppm and average count. The PRIREF or SECREF is considered valid if the frequency error between PRIREF / SECREF and XO is within the valid threshold. While it's frequency valid, it's considered as frequency invalid if the frequency error exceeds the invalid threshold. The accuracy in ppm indicates how accurate the valid and invalid threshold can be. In other words, this is the resolution of valid and invalid threshold counters. The minimum average count is 2. Keep it as 2 unless the reference clock has too much wander and the DPLL loop bandwidth is too narrow. In that case, raise the average count to no more than 10. As mentioned, the '0-error' reference for frequency detection is the XO. In reality, of course, the XO frequency is not '0-error'. Therefore, the valid and invalid thresholds must take the XO ppm error into account. The minimum valid threshold should be max XO frequency error + max PRIREF / SECREF frequency error + accuracy in ppm. The minimum invalid threshold should be valid threshold + accuracy in ppm.\n\n4. Early and late clock window detector. This detector is only valid for PRIREF / SECREF frequencies >= 2 kHz. 3 parameters are needed: early counter, late counter and number of missing clocks. After setting early and late counters, the T_early and T_late are calculated accordingly. As shown in the timing diagram, the PRIREF / SECREF is considered valid if its next clock edge falls within ideal next edge - T_early and ideal next edge + T_late. Setting the number of missing clocks to x is equivalent to adding x * reference_clock_period to T_late. So the number of missing clocks is typically set to 0 unless gapped clock needs to be supported. The early and late clock detector uses divided down BAW VCO frequency as its '0-error' reference. However, since this is a very coarse detection method (resolution of T_early and T_late counter is roughly 1.6 ns), the ppm error of the BAW VCO itself is not of concern.\n\n5. 1-pps phase detector. This detector is only valid for PRIREF / SECREF frequencies < 2 kHz. T_jitter is auto-calculated according to the phase detector counter. As shown in the timing diagram, the PRIREF / SECREF is considered valid if the next clock edge falls within ideal next edge - T_jitter and ideal next edge + T_jitter. Note that the '0-error' clock reference for 1-pps phase detector is the XO, so T_jitter must be greater than the sum of: (1) XO phase error accumulated through one PRIREF / SECREF clock period (for example, 1 second for 1-pps input). This includes the phase error caused by frequency inaccuracy, accumulated jitter as well as wander. (2) The max period jitter of PRIREF / SECREF. Therefore, low frequency and high stability XO is recommended for 1-pps input. This is because for XOs with the same frequency stability, the one with the lower frequency accumulates less phase error over fixed period of time. 12.8 MHz TCXO / OCXO is recommended for 1-pps input.
    DPLL_VCO_freq=2500
    bRUN_SCRIPT=Run Script
    btn_dpll_show_instructions=Show Instructions
    btn_page5_back=<BACK
    btn_page5_next=NEXT>
    btn_restore_dpll_reg=Restore Calculated DPLL Settings
    cb_show_dpll_registers=0
    combo_disable_fastlock=0
    combo_set_max_tdc_freq=0
    combo_switching_method=0
    sDPLL_LBW=100
    sDPLL_LBW_ACT=101.4
    sDPLL_PEAK=0.1
    sDPLL_PEAK_ERROR=1
    sMAX_TDC_freq=26000000
    sPRIREF_freq_display=10.0 MHz
    sSECREF_freq_display=Disabled
    sTDC_freq=10.0 MHz
    s_wizard_dpll_message_box=DPLL calculation completed!\n\nTDC frequency = 10000000\n\nPlanned VCO1 frequency = 2500000000\nActual VCO1 frequency = 2500000000\nPLL1 frequency error = 0 ppb\n\nPlanned VCO2 frequency = 6160000000\nActual VCO2 frequency = 6160000000\nPLL2 frequency error = 0 ppb\n\nDPLL fastlock time = 124.52 ms + 12.70 ms = 137.22 ms\n\nTotal DPLL frequency lock time ~= DPLL fastlock time + 2 * DPLL frequency lock measurement time\n\nTotal DPLL phase lock time ~= DPLL fastlock time + 2 * DPLL phase lock measurement time
    BAW_LOCK_PPM_THRESH=5
    BAW_UNLK_PPM_THRESH=10
    DPLL_PL_LOCK_calc=276.76 ps
    DPLL_PL_UNLK_calc=4.43 ns
    btn_baw_lock_detect_default=Set Default
    btn_dpll2_show_instructions=Show Instructions
    btn_dpll_freq_lock_detect_default=Set Default
    btn_history_recommend=Min Values Required
    btn_page6_back=<BACK
    btn_page6_next=NEXT>
    btn_ph_threshold_recommend=Recommended
    sBAW_LOCK_ACCURACY_PPM=1
    sBAW_LOCK_AVG=2
    sBAW_TMEAS_LOCK_calc=19.2000 ms
    sDPLL_HISTCNT_calc=52.43 ms
    sDPLL_HISTDLY_calc=33.59 ms
    sDPLL_LOCK_ACCURACY_PPM=1
    sDPLL_LOCK_AVG=10
    sDPLL_LOCK_PPM=1
    sDPLL_PL_MEAS_TIME=9.86 ms
    sDPLL_TMEAS_LOCK_calc=96.0000 ms
    sDPLL_UNLK_PPM=10
    s_wizard_dpll2_message_box=INSTRUCTIONS:\n\nAll lock detect settings are set to either default or recommended values after the DPLL script is run. Still, it is highly recommended to go through the instructions and make the adjustments.\n\n1. BAW frequency lock detect. Disable this if DPLL is enabled. This detector is only useful if the DPLL is disabled and the device works in free-running mode. Enter lock threshold in ppm, unlock threshold in ppm, average count (min value = 2) and accuracy in ppm. The BAW (VCO1) is considered to be locked if the frequency error between the BAW and the XO is within lock threshold. Once the BAW is locked, it's considered to be unlocked if the frequency error exceeds the unlock threshold. The step size of lock and unlock threshold in ppm = accuracy / average. If there's no specific requirement for BAW lock detect, click 'Set Default'.\n\n2. DPLL frequency lock detect. Enter lock and unlock thresholds in ppm, average count (min value = 2) as well as accuracy in ppm. The DPLL is considered to be frequency locked if the frequency error between the VCO1 and the references is within the lock threshold. While the DPLL is frequency locked, it's considered to be frequency unlocked if the frequency error exceeds the unlock threshold. The step size of lock and unlock threshold =  accuracy / average. If there's no specific requirement for DPLL frequency lock detect, click 'Set Default'.\n\n3. DPLL phase lock detect. Set lock and unlock threshold counters. The actual lock and unlock thresholds in second are then calculated accordingly. The DPLL is considered as phase locked if the phase difference between the two inputs of TDC (divided reference and divided VCO1) is within the lock threshold. While the DPLL is phase locked, it's considered as phase unlocked if the phase difference exceeds the unlock threshold. Use recommended values for this. The lock and unlock counters should not be manually set, and they are only used for engineering debugging purposes.\n\n4. Tuning word history. This block sets the tuning word history for holdover. Set history counter and delay counter. The averaging time and delay time are then auto-calculated. Refer to datasheet section '9.3.7.4 Tuning Word History' for details. If there's no specific requirement for holdover tuning word, click 'Min Values Required'. This makes sure that the delay time is more than 8 times of the reference frequency validation measurement time, and that the averaging time is longer than the delay time.
    btn_page7_back=<BACK
    PLL1_24b_DEN=572605
    PLL1_24b_NUM=5120
    PLL1_DEN=1099511627776
    PLL1_PFD_freq=48.0048
    VCO1_freq=2500
    XO_freq=48.0048
    PLL2_DEN_fixed=16777216
    PLL2_PFD_freq=138.8888888889
    VCO1_freq=2500
    VCO2_freq=6160
    XO_freq=48.0048
    MUTE_DPLL_FRLOCK=1
    OUT0_freq=140.0 MHz
    OUT1_freq=140.0 MHz
    OUT2_freq=140.0 MHz
    OUT3_freq=140.0 MHz
    OUT4_freq=100.0 MHz
    OUT5_freq=100.0 MHz
    OUT6_freq=100.0 MHz
    OUT7_freq=100.0 MHz
    PLL2PDIV1_freq=1540
    PLL2PDIV2_freq=1540
    VCO1_freq=2500
    VCO2_freq=6160
    sOUT7_DIV=25
    AbsDCO_ppb_error=0.01
    DPLL_DCO_FREQ_PPB_ACT=0
    DPLL_DCO_STEP_ACT=0
    DPLL_REF_NUM_calculated=549755813888
    bDPLL_FDECR=Decrement
    bDPLL_FINCR=Increment
    bResetNumerator0ppb=Reload Original DPLL Numerator
    cbDCO_MODE=1
    sDPLL_DCO_STEP=0.01
    sSYNC_PHASE_OFFSET=
    bClearAllFlagStickyStatus=Clear All Flags
    bReadStatus=Read Status
    ADDR_10=200
    ADDR_11=0
    ADDR_249=0
    ADDR_250=0
    ADDR_251=0
    ADDR_252=0
    REGCOMMIT_PG=0
    bEXPORTEEPROMFILE=Export GUI Map --> EEPROM File
    bIMPORTEEPROMFILE=(1b) Import EEPROM File --> GUI Map
    bLoadDefaultEEPROMImageToGUIMap=(1c) Load Default EEPROM Image --> GUI Map
    bLoadPage_from_GUIMap_to_GUI_Registers=Load GUI Map PAGE --> Register
    bPROGRAMEEPROM=(3) Program EEPROM <-- SRAM
    bREADBACKEEPROM=Read All EEPROM --> GUI Map
    bREADBACKROM=Read All ROM --> GUI Map
    bREADBACKSRAM=Read All SRAM --> GUI Map
    bREG2EE=(1a) Commit Registers --> SRAM PAGE/GUI Map
    bUpdate_ExtraEEPROM_Bytes=Read Extra\nEEPROM Bytes
    cbEESLAVEADR=0
    cbWrite_ADR10=0
    cbWrite_ADR11=0
    mtc_EEPROMdump=
    mtc_USERNOTES=Enter User Notes
    tc_DESIGNNAME=Enter Design Name
    bButton1=Builtins
    bButton2=Globals
    bButton3=Button 3
    bButton4=ReLoad Scripts
    bButton5=Button 5
    bClear=Clear
    bEnter=Enter
    bLoadButton=Load Script
    bSetButton=Set Script
    bSystemUpdate=SystemUpdate
    bSystemUpdateRunOnce=SystemUpdateRunOnce
    cbButtonSelect=0
    mtcOutput=UpdateStatusBar("Hello World")
    mtcScript=0
    tcInput=UpdateStatusBar("Goodbye World")
    tcLHS=0
    

    Your assistance is appreciated.

    Regards,
    Carlo

  • Ok, thanks for the info.  We'll review it and update you.

    73,
    Timothy

  • Hello Timothy,

    Do we have an update? Your help is appreciated.


    Regards,
    Carlo

  • Hi Carlo,

    Please find my comments below:

    1. The attached report compares 140MHz spectrum with 100MHz spectrum. This is not making much sense because 140MHz is LVDS but 100MHz is LVCMOS. LVCMOS amplitude is much higher than LVDS, so when you look at the two in a spectrum analyzer, the noise floor as well as carrier power level will for sure be different. So for a sanity check, use 100MHz for both or 140MHz for both. Make apple-to-apple comparison. Of course when using a phase noise analyzer, the output amplitude does not affect phase noise, but since this is spectrum analyzer which can't measure the true phase noise, this is very likely related to output amplitude.

    2. When DPLL is locked, BAW lock status is unimportant. The BAW unlock status (doesn't mean it's really unlocked) is likely due to the frequency accuracy of the XO. For sanity check, measure the XO frequency with a frequency counter, then change the XO frequency in the wizard to its true frequency. Alternatively, change the BAW lock/unlock threshold. For example, lock/unlock = 50/70ppm.

    Regards,
    Hao