LMX2492EVM: Wide bandwidth chirp

Part Number: LMX2492EVM
Other Parts Discussed in Thread: LMX2492

Hi,

I'm looking to generate a 9.6Ghz - 11 Ghz chirp signal (linear frequency ramp) for an FMCW radar application. The chirp

seems to be working fine at lower bandwidths but I seem to getting strange signal

artifacts that do not resemble a chirp when trying to generate 9.6-11Ghz. I'm using

the onboard clock with TICS Pro currently. Are there any issues with this sort of bandwidth

on the board? I also plan to down convert this chirp with a mixer. 


Thanks

  • Hello Jay,

    Would it be possible to share the TCS file you are using to generate the chirp?

    73,
    Timothy

  • Hi Timothy,

    I'm essentially just setting the LMX2492 PLL. Setting up the default configuration. And changing the values in the ram calculator from 9600Mhz to 11000 Mhz while enabling ramp and RST.

    0488.HexRegisterValues.txt
    R141	0x008D00
    R140	0x008C00
    R139	0x008B00
    R138	0x008A00
    R137	0x008900
    R136	0x008800
    R135	0x008700
    R134	0x008600
    R133	0x008500
    R132	0x008400
    R131	0x008300
    R130	0x008200
    R129	0x008100
    R128	0x008000
    R127	0x007F00
    R126	0x007E00
    R125	0x007D00
    R124	0x007C00
    R123	0x007B00
    R122	0x007A00
    R121	0x007900
    R120	0x007800
    R119	0x007700
    R118	0x007600
    R117	0x007500
    R116	0x007400
    R115	0x007300
    R114	0x007200
    R113	0x007100
    R112	0x007000
    R111	0x006F00
    R110	0x006E00
    R109	0x006D00
    R108	0x006C00
    R107	0x006B00
    R106	0x006A00
    R105	0x006900
    R104	0x006800
    R103	0x006700
    R102	0x006600
    R101	0x006500
    R100	0x006400
    R99	0x006300
    R98	0x006200
    R97	0x006100
    R96	0x006000
    R95	0x005F00
    R94	0x005E00
    R93	0x005D00
    R92	0x005C04
    R91	0x005B27
    R90	0x005A10
    R89	0x005900
    R88	0x005800
    R87	0x00575B
    R86	0x0056C0
    R85	0x005500
    R84	0x005400
    R83	0x005300
    R82	0x005218
    R81	0x005100
    R80	0x005000
    R79	0x004F00
    R78	0x004E7A
    R77	0x004D00
    R76	0x004C00
    R75	0x004B00
    R74	0x004A00
    R73	0x004900
    R72	0x004800
    R71	0x004700
    R70	0x004600
    R69	0x004500
    R68	0x00447E
    R67	0x004300
    R66	0x004200
    R65	0x004100
    R64	0x004000
    R63	0x003F02
    R62	0x003E00
    R61	0x003D00
    R60	0x003C00
    R59	0x003B00
    R58	0x003A01
    R57	0x003900
    R45	0x002D00
    R44	0x002C00
    R43	0x002B00
    R42	0x002A00
    R41	0x002900
    R40	0x002800
    R39	0x002752
    R38	0x002618
    R37	0x002510
    R36	0x002408
    R35	0x002341
    R34	0x002204
    R33	0x002120
    R32	0x002000
    R31	0x001F32
    R30	0x001E0A
    R29	0x001D00
    R28	0x001C1F
    R27	0x001B08
    R26	0x001A00
    R25	0x001901
    R24	0x001800
    R23	0x001703
    R22	0x0016E8
    R21	0x001500
    R20	0x001400
    R19	0x001300
    R18	0x00122C
    R17	0x001100
    R16	0x001060
    R15	0x000F00
    R14	0x000E00
    R13	0x000D00
    R12	0x000C00
    R11	0x000B00
    R10	0x000A00
    R9	0x000900
    R8	0x000800
    R7	0x000700
    R6	0x000600
    R5	0x000500
    R4	0x000400
    R3	0x000300
    R2	0x000201
    R1	0x000100
    R0	0x000018
    

  • Hi Jay,

    The on-board VCO requires >7V tuning voltage in order to output 10.5GHz. You have to modify the EVM to use active filter to support >5V tuning voltage. Check EVM user's guide for the EVM schematic.

  • Hi Noel,

    Thank you for the answer and I was wondering if you could provide some more details on how to get the tuning voltage up to 7volts.

  • Hi Jay,

    Please read Chapter 41 of this book for details of active loop filter. https://www.ti.com.cn/cn/lit/ml/snaa106c/snaa106c.pdf

    You may use PLL Sim to do an active filter design. https://www.ti.com/tool/PLLATINUMSIM-SW

  • Hi Noel,

    Thank you for the information. I actually need to generate a waveform from 5.5-7Ghz. I was wondering if I still need to modify the tuning voltage to achieve this. If not, what would I need to change in the TICS Pro to achieve this. Is there any way I can generate a 1 or 1.5Ghz bandwidth chirp without using the active filter design? Thanks

  • Hi Jay,

    From the VCO datasheet, we might be able to do a 1 GHz chrip (9GHz to 10GHz output) with passive loop filter. 

  • This sounds great. Since by default the VCO ramp starts at 9.6Ghz. Is there a recommended configuration to change the ramp start to 9Ghz?

  • Also, another question is that my chirp that I'm currently using from 9.6-9.7Ghz only appears on the RFout/2 port and not the RFout port. I'm wondering why this is happening.

  • Hi Jay,

    Both RF and RF/2 output are active, make sure you are not measuring the VCO fundamental signal from RF/2 port. 

     To get ramp started at 9GHz, put 9000 in the VCO frequency box in PLL page.

  • Hi Noel,

    This seems to make sense. However, I seem to be having a small issue. I'm currently generating a 9-10Ghz chirp for an FMCW application. I'm currently sending everything through a wire and am mixing the chirp signal with itself. The output I'm getting should look sinusoidal; however, I'm getting the result below. Some of the leakage at the edges makes sense due to PLL reset but I'm wondering why the signal isn't sinusoidal. I'm wondering if this is an issue with the chirp.

  • Hi Jay,

    I do not understand what is "sending everything through a wire and am mixing the chirp signal with itself", can you share the connection diagram?

    BTW, did you get correct chirp directly from the EVM (without mixing)?

  • Hi Noel,

    I'm not entirely sure if the chirp is correct since I cannot directly sample the waveform's high sampling frequency. This is the block diagram of the setup I'm currently using. I'm sampling the down converted signal which should be a sinusoid if the chirp is fully generating properly.

  • Hi Noel,
    The chirp looks like it is working thank you for your help. One last question I have is if I want to feed a 30Mhz external reference clock to the chirp generator instead of using the onboard 100Mhz clock, will I have any issues generating this same 9-10Ghz FMCW waveform?

  • Hi Jay,

    If you use 30MHz reference clock, the max. fpd you can use is 60MHz. Without modifying the loop filter, the loop bandwidth will be smaller than the EVM default, depending on how fast you sweep the frequency, lower fpd may or may not have any impact to the ramp.