Clock & timing forum - Recent Threads

LMK1C1102: LMK1C1102 Unused Outputs

MP — Tue, 19 May 2026 20:05:25 GMT

Part Number: LMK1C1102

In the datasheet for the LMK1C1102, it says pins 5 and 7 are not connected (NC), and unused outputs can be left floating. Is it ok to gorund these pins instead?

LMK04832: PLL Failing to lock at certain phase detector frequencies

Justin Soliman — Tue, 19 May 2026 17:29:03 GMT

Part Number: LMK04832

Hello,

We've been using the LMK04832 in PLL2, internal VCO1 single PLL mode in our radio's clock tree for the LO input of our upconverter for about 2 years with a 122.88MHz input and 122.88MHz output. In the image below, PLL1 is enabled in the registers, but not used in our design, TICS file: nominal_LMK04832.tcs. Our loop filter looks like this:

We recently discovered that we were having micro unlocks at cold (<-10C) in our clock tree leading to data loss at high symbol rates. It manifested as both ~1db drops in power over ~10us span (caught using zero span mode of spectrum analyzer) and the phase spinning around in the constellation plot (at cold but not room temp). This prompted an investigation, and in that investigation I tried varying the phase detect frequencies of the LMK04832 while using the same 122.88MHz input in our design. In our design we use the SI5345 with a TCXO input as our clock generator that feeds the LMK among other things. I found that the PLL would entirely fail to lock at room temperature at 12.288, 24.576 and 40.96MHz phase detect frequency (tested by using CLKin0 R divider). Oddly enough, it was able to lock at 30.72MHz for some reason. I then fed a 50MHz TCXO into the LMK04832 CLKin1 input (through PN: SN65LVDS9638D LVDS driver, all else in design held constant except with a 125MHz output), and it still failed to lock at room temp (TICS file: Fin_50MHz_LMK04832.tcs). I confirmed that the signal going into CLKin1 was clean, and >500mVpp differential. I then tried changing the resistor in the loop filter shown above from 330 Ohm to 1kOhm as PLLatinum SIM indicated that would increase the phase margin in the 50MHz input case (had PLLatinum SIM optimize for jitter), but it still failed to lock at room temp.

Ultimately I would like to resolve the micro unlock at cold issue, but I feel that resolving the failure to lock at lower phase detector frequencies will help guide me there as those instabilities may be related. So for now I would like help getting the LMK04832 to work with different phase detector frequencies, thank you!

LMK00105: Need similar IC

Thrinesh S — Tue, 19 May 2026 13:52:44 GMT

Part Number: LMK00105

Hi Team,

Please provide a similar IC to the LMK00105 with a 2-channel LVCMOS fanout buffer that supports a 25 MHz clock input and crystal input support.

LMX2820: Confirm multiple LMX2820 Chips can use same MUXOUT line

Cole Harlow — Tue, 19 May 2026 13:26:28 GMT

Part Number: LMX2820

Hello, per the answer to the lniked question the MUXOUT pin of the 2820 can be placed on the same bus as multiple other LMX2820s as long as the R3 register is used to set the chip accordingly. The answer ends by stating there a plans to integrate this information into the datasheet/register maps for the part, but when I check these sources I am unable to find any indication that this is how the parts operate.

I am working on a quad channel chip where we plan to have four LMX2820s operating. My intent is to have all of them use the same MUXOUT line and disable/enable as needed

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1007783/lmx2820-muxout-pin-tri-state

LMX2572LPEVM: Evaluating the PLL lock time of the LMX2572LPEVM

ishii.takeshi — Tue, 19 May 2026 10:16:15 GMT

Part Number: LMX2572LPEVM

I am evaluating the PLL lock time of the LMX2572LPEVM. I measured the time vs. frequency ratio when changing the frequency from 100MHz to 125MHz.

The frequency change method was as follows:

* Changed the N-divider value from 32 to 40

* Clicked VCO calibration

The following two issues were anticipated:

(1) PLL lock time was slightly less than 60us

(2) A glitch occurred around 85us

Regarding (1), I thought it was too slow. The datasheet boasts a lock time of 20us.

To avoid the glitch in (2), a PLL lock time of around 90us is necessary.

Are there any solutions to the issues in (1) and (2)?

Incidentally, the oscilloscope used for the measurement was a Trotechnics MSO64B, 10GHz type.

LMK1C1104: (Part2) Recommended clock buffer for distributing one 8MHz clock to four MCUs

Conor — Tue, 19 May 2026 09:30:28 GMT

Part Number: LMK1C1104

Hi,

I am reposting this because the original thread has not received any response, and there seems to be a bug preventing me from replying to that thread.

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1645367/lmk1c1104-recommended-clock-buffer-for-distributing-one-8mhz-clock-to-four-mcus

Could you please let me know if there are any updates on this question?

Thanks,

Conor

CDC6C: replacement confirm

Allen Lu — Tue, 19 May 2026 07:08:25 GMT

Part Number: CDC6C

hi team,

would you help to confirm these part is oaky to replace ?

OSC, 40 MHz, 3.3 V, SMD

2.5x1x2.5mm

625L3C040M00000

CTS Electrocomponents

attached the datasheet link : https://www.ctscorp.com/Files/DataSheets/Passives/FCP/Clock-Oscillators/clock-ocillators-625-datasheet.pdf

CDC6CE040000ADLER

CDC6CE040000ADLFR

LMK04610: calculating the loopbandwidth

gurudatta p — Tue, 19 May 2026 05:47:07 GMT

Part Number: LMK04610

LMK04610 is not shown in Pllatinum SIM software, so how to calculate loopbandwidth,
In Tic's pro they are just asking to mention bandwidth
why pllatinum sim does't have lmk04610, then how to get overall phase noise and rms jitter

TLC555: about PCN:20260217004.1

R.Fukunaga — Tue, 19 May 2026 04:23:14 GMT

Part Number: TLC555

Hi all,

I have a question about PCN of TLC555.

PCN: Die Rev has been changed in 20260217004.1.

PCN_20260217004.2_Change_Notification.pdf
Did you revise the Rev of DL-LIN products from F to B?

And why? Can you tell me the background?

I understand the flow of PCN as follows.

In PCN in 2023, RFAB was added.
Die Rev F→A (RFAB added)

In PCN in 2026, characteristics were improved.
Die Rev F→B (Die Rev changed)

Does PCN in 2026 refer to the change from F to B of 150 mm in the Dallas factory?

Best Regards,

Ryusuke

AM62A7-Q1: CAN clock source

liu xiwen — Tue, 19 May 2026 01:57:53 GMT

Part Number: AM62A7-Q1
Other Parts Discussed in Thread: AM62A74

Hi,teams

I consulted our software engineer. In AM62A74, the clock source for CAN has been fixed and cannot be configured. Could you please clarify whether the clock input source for CAN is derived from the external main crystal oscillator? Or it still originates from the high-speed clock within the SOC or the frequency division of the PLL (phase-locked loop)

Thanks,

Xiwen

LMX2594: phase synchronization of 2 LX2594 output

Yoda Yukihide — Mon, 18 May 2026 09:49:44 GMT

Part Number: LMX2594

Question:

Could you please advise on the necessary settings and design considerations to achieve this design goal?

Our design goal:

In the following hardware configuration, we would like to achieve phase synchronization by setting the final stage to 1638.4MHz and 4096M.

(Phase synchronization definition: Synchronization of 5 periods of 1638.4MHz and 2 periods of 4096M as below figure)

We have confirmed via oscilloscope observation that the 102.4MHz input to PLL1/PLL2 is synchronized in current H/W.

Could you please advise on the necessary settings of LMX2594 and design considerations to achieve this design goal?

We have also attached our proposed settings in a below table, so we would appreciate it if you could check for any problems with these settings.

In particular, we would appreciate answers to the following:

1. Is it necessary to make the lengths from LMK00304S to PLL1/PLL2 equal?

2. Is synchronization possible even without using the Sync Buffer?

Setting Table

Register / Parameter	PLL1 config	PLL2 config	Remarks / Common Conditions
OSC_2X	0	0	Doubler disabled
MULT	1	1	Multiplier bypassed
PLL_R_PRE	1	1	R pre-divider
PLL_R	1	1	R divider (fPD = 102.4 MHz)
PLL_N (R36)	96	80	N divider (Integer-N mode)
MASH_ORDER	0	0	Fractional disabled (Integer mode)
CHDIV (R75)	code 2 (/6)	code 0 (/2)	Channel divider
SEG1_EN	1	1	Segment 1 enabled (*Verify for Config 2)
OUTA_MUX / OUTB_MUX	0	0	Channel divider output
OUTA_PWR	19	19	Output power setting
OUTB_PWR	29	29	Output power setting
OUT_ISET	0	0	Max output current setting
OUTA_PD / OUTB_PD	0	0	RFoutA / RFoutB output enabled
MASH_RESET_N	1	1	MASH reset released
POWERDOWN	0	0	Normal operation
RESET	0	0	Reset released
FCAL_EN	1	1	VCO calibration enabled
VCO_PHASE_SYNC	0	0	Phase sync disabled
RAMP_EN	0	0	Ramp (frequency sweep) disabled
MUXOUT_LD_SEL	1	1	MUXout pin: Lock Detect output
CPG	7	7	Charge pump current: 15 mA
SYSREF	Disabled	Disabled	SYSREF output unused
INPIN_IGNORE	1	1	External input pin settings ignored
VCO Frequency	9.8304 GHz	8.1920 GHz	Calculated value (Within 7.5 to 15 GHz range)
RFoutA / B Frequency	1.6384 GHz	4.0960 GHz	Final output frequency

CDCDB800: [AGC ]CDCDB800RSLR design questions for AE confirmation

SHH — Mon, 18 May 2026 09:39:42 GMT

Part Number: CDCDB800

Hi AE Team,

We received some questions from the customer regarding CDCDB800RSLR. Could you please help confirm the points below?

1. For the SMBWRTLOCK pin, if it is left as NC, will it impact system stability?
Is there any chance it may cause abnormal behavior during power-up or in a noisy environment?
Would you recommend tying this pin to High or Low instead of leaving it floating?
2. From the datasheet block diagram, we cannot clearly confirm whether this device has an internal PLL architecture.
Could you please confirm whether CDCDB800RSLR supports PLL mode / bypass mode, or any similar mechanism?

3. For the PLL BW values shown in the datasheet additive jitter table, our understanding is that these are the external PCIe spec filter conditions used during additive jitter measurement, not internal adjustable PLL parameters of this IC.
Could you please confirm if this understanding is correct?

4. If the PLL BW is only a measurement condition, would the propagation delay of this device have any impact on PCIe link training margin, or possibly cause link training failure?

Customer would also like AE’s suggestion for schematic adjustment reference.

Best regards,

PLLATINUMSIM-SW: Unable to downlaod

manoj chugh — Mon, 18 May 2026 09:19:21 GMT

Part Number: PLLATINUMSIM-SW

Access denied to download software

LMK04832-SP: Question on lead trimming / forming support for LMK04832-SP package

Jared Wu — Mon, 18 May 2026 08:17:44 GMT

Part Number: LMK04832-SP

We are currently evaluating LMK04832-SP for a space-related application.

footprint need to cut long pin to short pin from 29x29 mm to 10.9x10.9mm

Our customer is reviewing the package dimensions and asked whether the external leads could be shortened to better fit our mechanical constraints.

Before making any design decision, we would like to clarify the proper process from TI’s perspective:

Does TI offer any factory-side lead trimming / lead forming service before shipment?
If TI does not provide this service, can customers perform lead trimming during PCB assembly / SMT process?
If customer-side trimming is allowed:
- what is the recommended method?
- is there a minimum lead length requirement?
- are there any tooling/process recommendations?
Would such lead trimming/forming impact:
- package reliability
- hermetic sealing
- radiation qualification / RHA compliance
- warranty/support coverage
Has TI previously supported similar requests for this package type?

We want to ensure any package modification follows TI’s recommended handling guidelines.

LMX2572: LMX2572 output skew between RFOUTA and RFOUTB(used as SYSREF)

wenhao Huang — Mon, 18 May 2026 07:55:21 GMT

Part Number: LMX2572

Hi experts,

We want use LMX2572s in our project as a precise auto-aligned SYSREF generators, RFOUTA will be connected to time difference measure circuit, and output a 125MHz clock for multi parts time difference measuring, and RFOUTB used as SYSREF output port, a 7.8125MHz will be used (which is 125MHz/16). Therefore, the time skew between RFOUTA and RFOUTB will be very important for that function working appropriately. We want know what is the maximum skew between these two ports under the condition above could be (over different temperature, different parts etc.)

Our configuration is shown in the following figure.

LMK04828: clock configuration in Uboot on AFE8030 EVM

vamsi bolla — Mon, 18 May 2026 06:12:41 GMT

Part Number: AFE8030EVM
Other Parts Discussed in Thread: LMK04828, AFE8030,

We are configuring LMK04828 from Linux and U-Boot in an Agilex + AFE8030 setup.

LMK configuration from Linux works and AFE relink succeeds.
But when configuring the same LMK registers from U-Boot using sspi,it is not locking and even returning FFFFF.

In Linux flow, we perform:

->I2C pre-sequence->CPLD unlock ->SPI mux switch to LMK ->LMK SPI writes ->SPI mux switch back to AFE

Is there any additional timing/reset/PLL lock/SYSREF sequence required when configuring LMK04828 from U-Boot?

LMK04832: PCB Trace Length Matching Requirements for LMK04832 + LMX2594 in JESD204B Design

XH Y — Mon, 18 May 2026 06:05:34 GMT

Part Number: LMK04832
Other Parts Discussed in Thread: LMX2594

Hi TI Team,

I am designing a JESD204B clocking tree using the LMK04832 and LMX2594. Due to specific sampling frequency requirements, I must utilize both chips in my system.

I have a few questions regarding the PCB layout and trace length matching, specifically concerning the relationship between the high-frequency clock and the various clocks output by the LMK04832.

System Configuration:

Clock Generator: LMK04832
High-Frequency Synthesizer: LMX2594 (generating a 1.8 GHz clock)
Protocol: JESD204B

My specific questions are:

Trace Length Matching: What are the specific requirements for trace length matching between the 1.8 GHz clock (from LMX2594) and the Device Clock / SYSREF pairs (from LMK04832)?
Phase Alignment: Since the 1.8 GHz clock is the primary sampling clock, how should I manage the skew between it and the lower-frequency clocks output by the LMK04832 to ensure JESD204B Deterministic Latency is maintained?
Layout Best Practices: Are there recommended tolerances (in mils or mm) for these trace relationships to avoid timing violations across multiple clock domains?

Any guidance on the routing constraints for this dual-chip architecture would be greatly appreciated.

Thanks in advance!

LMK04832: No clock output when LMK04832 operates in Single Loop mode or Distribution

?? ? — Mon, 18 May 2026 03:38:37 GMT

Part Number: LMK04832

Hi,

On my board, LMK04832 has CLKIN0 connected to the 3.84 MHz , and CLKIN1 connected to the 245.76 MHz from the previous PLL. OSCIN is left unused. I want to output clocks in single PLL2 mode or Distribution mode. However, no clock frequency can be detected on any output pins regardless of configuration settings.

All register read/write operations of the host controller for the LMK04832 are configured correctly. The input clock signals and reset signals are also working normally.

Please help check my configuration file, the attachment file.

LMK04832#1-SINGLE-PLL2.zip LMK04832#1-Distribution.zip

NE555: Power reset with switch press

Pradeep Patel — Sun, 17 May 2026 15:57:46 GMT

Part Number: NE555
Other Parts Discussed in Thread: TLC555

Hi,

I am designing at circuit to generate a power reset signal which will turn off a P-Channel MOSFET to cut off the power to remaining circuit on board. Power reset will be generated by pressing at switch. If the switch is pressed for < 2s then there will not be any effect on system power. If the switch is pressed for > 2s then it will turn off P-Channel MOSFET for minimum 5s or till the switch is pressed. After that reset signal will be withdrawn and P-Channel MOSFET will turn on.

I am planning to use Dual NE555 timer chip to design this logic circuit. For the first part I will use one timer as below:

Please confirm if my understanding of output pulse generation is correct. Output will go low after 2s of switch pressed. If switch is pressed for <2s then output will remain high. After output goes low it will turn high only when switch is released.

Thanks,

Pradeep

AM2732: AM2732: How do I switch the clock source for an MCASP instance in my application?

Xiang Zhao — Sun, 17 May 2026 11:38:45 GMT

Part Number: AM2732

However, the AM273x Technical Reference Manual does not mention any "glitch-free switching between the local and system AUXCLK source" mechanism, unlike what appears to be available on AM275x.

My question: What is the recommended procedure to switch the MCASP clock source at runtime on AM2732?

Specifically, I would like to know:

Does the AM2732 clock mux for MCASP support glitch-free switching, or must the MCASP be stopped before changing the clock source?
If a stop-reconfigure-restart sequence is required, what is the correct order of operations to avoid DMA descriptor corruption or audio buffer data loss?
Are there any application notes or SDK examples targeting AM2732 that demonstrate this use case?

Any guidance or pointers to relevant documentation would be appreciated.

LMK1D1208EVM: CAD model (.step file)

Sam Fakour — Fri, 15 May 2026 18:56:43 GMT

Part Number: LMK1D1208EVM

Can TI please provide a CAD model/.step files for this board

CDCVF25081: Power up time requirement and 25-ohm Damping Resistor

Jennifer H — Fri, 15 May 2026 17:10:34 GMT

Part Number: CDCVF25081

Hello,

Does CDCVF25081PW have any requirements for power up time for all VDDs to reach minimum specified voltage?
Does TI make a version of CDCVF25081PW without the 25-ohm damping resistor?

Thanks!

CDCEL937: Frequency Resolution

Glen Alvis — Fri, 15 May 2026 15:35:05 GMT

Part Number: CDCEL937
Other Parts Discussed in Thread: CLOCKPRO,

We are using the CDCEL937PWR as a baud rate generator for RS422 communication. It has 9 outputs but I only need 6. Our design consultant has chosen either a 100MHz or a 29.49MHz clock as the input frequency. Unfortunately if one of these two is chosen it cannot be changed. I have downloaded the ClockPro software and I am having trouble acheving the baud rates that I require.

Here are the baud rates (yes, they are slow):

1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200

Can they be obtained with the CDCEL937PWR?

LMX2594: The device locks and after some time unlocks

Gabriel Santos — Thu, 14 May 2026 15:16:30 GMT

Part Number: LMX2594

Hello.

I have a design with the LMX2594 that should be locking at 7.26GHz.

I have tested the design in more than one board and I have experienced after some time working under harsh conditions, the output frequency to shift from the desired frequency to a frequency ~100MHz to the left, and keeps drifting around it. This seems to me, related to temperature rise.

Recently, this is happening ~30s-1m after turning on, in situations that it would never happen. I have tested to improve the margin phase of the loop filter from 48º to 65º, as it could be the filter to be unstable, but without success.

I am using the following configuration.

CDCE6214: Design review

JH Shin — Thu, 14 May 2026 06:43:15 GMT

Part Number: CDCE6214

Hello,

My customer requests a design review for CDCE6214RGER.

Please review the design of the file below to see if there are any issues.

CDCE6214RGER_260514.zip

Thank you.