Clock & timing forum - Recent Threads

CDCDB803: The technology issue for CDCDB803ERSLR

Zhang Liang — Mon, 12 Oct 2026 13:10:33 GMT

Part Number: CDCDB803

Hi,

We use CDCDB803ERSLR for the clock buffer and we have below issue:

If using 2 BUFFER chips: Can the CKPWRGD_PD# signals of these 2 clock BUFFER chips be controlled by a single signal?
Regarding the SMBUS ADDRESS Pin: SADR0/SADR1, if a Middle Level voltage is selected, can a design using a 2K pull-up and a 2K pull-down be adopted?
Plesae comfirm if we can use the below solution for the mid-level voltage:

CDCE6214-Q1: CDCE6214

linli shi — Mon, 12 Oct 2026 10:43:35 GMT

Part Number: CDCE6214-Q1
Other Parts Discussed in Thread: CDCE6214

Hello, I would like to consult about the use of CDCE6214. At present, I cannot realize the control of CDCE6214 chip. In detail: In order to bypass the reading and writing of eeprom, only the register set of the chip is written. At the same time, HW_SW_CTRL and REFSEL have been connected to the MCU on the hardware circuit, so the IO pins connected to the MCU are configured to high resistance state to realize the dangling state of HW_SW_CTRL and REFSEL. Let the chip enter the backoff mode. The voltage of the two pins measured by the multimeter is 1.6V, so it is confirmed that the state is M and the backoff mode has been entered. Then I used IIC to write the CDCE6214RGER register, but after a lot of tests, only a few registers were written correctly, and the values of the other registers were not the values I set. For example, the operation of first pulling PDN and then reading and writing register R43 can realize the reading and writing of the register, which shows the timing correctness of IIC, but when writing other registers, most of them have errors. In addition, the register group values (R0-R85) are obtained by TICSPRO software. Therefore, I would like to ask if there is anything else I have not considered. I hope to get a reply,thank you.

CDCLVC1104: Clock fanout timing limits for STM32H743 SAI outputs

Jonathan Reichardt — Sat, 10 Oct 2026 08:38:24 GMT

Part Number: CDCLVC1104
Other Parts Discussed in Thread: SN65LVDS31, , LMK1C1104

Hello,

We are selecting clock buffers for BCLK and frame sync in a modular audio system.

The source is an STM32H743 operating at 3.0 to 3.6 V, with GPIO speed setting 10 and I/O compensation enabled. Its datasheet specifies a maximum rise and fall time of 2.8 ns with a 30 pF load.

BCLK is 12.288 MHz or 6.144 MHz. Frame sync is 96 kHz or 48 kHz. The intended ambient temperature is -20 to +85 degrees C.

The proposed path is:

STM32 output -> local clock buffer -> SN65LVDS31 inputs.

Each clock-buffer output would drive one nearby SN65LVDS31 input through a short PCB trace with a series damping resistor.

CDCLVC1104 specifies a recommended input slew rate of 1 to 4 V/ns. The MCU edge-time specification does not establish that minimum slew rate.

Please clarify:

1. Are guaranteed minimum and maximum propagation delay and pulse-width distortion limits available for CDCLVC1104 at input slew rates below 1 V/ns? If no guaranteed timing applies, please confirm this.

2. Could LMK1C1104 provide an alternative? Please provide applicable minimum and maximum propagation delays for both rising and falling transitions, including the input-slew and output-load conditions. We would keep its supply within its specified 3.3 V range.

3. CDCLVC1104 specifies a maximum output transition time of 0.8 ns measured from 20 to 80 percent. The SN65LVDS31 timing fixture specifies generator rise and fall times of at most 1 ns. What measurement interval applies to that driver fixture? Can these specifications establish timing compatibility between the two devices?

4. Is a maximum SN65LVDS31 logic-input capacitance available for load calculation?

5. If neither clock buffer provides applicable guaranteed limits, which TI alternative would you recommend for this source, with specified minimum and maximum delay and pulse-width distortion?

We can adjust local placement and damping resistors. We need applicable electrical limits before selecting the parts.

Kind regards,
Jonathan Reichardt

LMK03318: Register Map in Data Sheet vs. Exported Hex Values from TICS

Tim Tewalt — Fri, 09 Oct 2026 19:38:40 GMT

Part Number: LMK03318

I am handing off my clock design to the software team and see that Register Map in LMK03318 datasheet does not match values I exported from TICSPro. What is the correct process to resolve the differences? Thank you. Tim HexRegisterValues.txt

LMK5C23208A: IDD_DPLL supply pin

Bernhard Boehmer — Fri, 09 Oct 2026 11:15:19 GMT

Part Number: LMK5C23208A
Other Parts Discussed in Thread: LMK5C33414A

Hello TI,

According to snas918, the LMK5C23208A has a current consumption of 55mA per DPLL:

What pin in this current drawn from, please? VDD_DIG or VDD_IN[1:0] perhaps?

Similar uncertainty seems to exist for other parts in the clockgen family, e.g. LMK5C33414A, etc.

LMK03001: The value and variation of the internal pull-up resistor

user6004480 — Fri, 09 Oct 2026 09:37:22 GMT

Part Number: LMK03001

Hi expert,

What are the value and variation of the internal pull-up resistor implemented at the SYNC* pin and GOE pin?

LMX2820: No output detected after calibration

Roberto Rebello — Wed, 07 Oct 2026 20:12:59 GMT

Part Number: LMX2820
Other Parts Discussed in Thread: LMX2594,

Hello,

I'm trying to configure a LMX2820 to generate a 9 GHz clock and a 5.86 MHz sysref. The LMX is working with the internal VCO and a 100 MHz OSCIN signal. Fpd is configured to 200 MHz, with OSC_2X enabled and 45 divider on PLL_N. SPI communication was configured, on an external FPGA, based on LMX2594 (as per this post) and registers were configured, after software reset, based on this document.

I can confirm that the LMX2820 recieves SPI commands. Writes to R0 POWERDOWN bit have significant current change. However, no readback is returned on MUXOUT. LMX2594's datasheet has a register to configure MUXOUT output, but I found no equivalent for LMX2820.

After configuration and calibration start, PLL never locks and no output is detected. During configuration a signal at 5.564 GHz is output on channel B, but disappears after FCAL_EN is set to 1. MUTE is grounded, but setting PINMUTE_POL to 0 also makes the output disappear. Changes to CHDIVB change the output as expected.

Setting VCO_SEL_FORCE to 1 and changing VCO_SEL, only outputs signals if CORE 1 is selected. All other configurations produce no output.

I've attached the configuration sent to the LMX2820 before calibration, as well as the connections on the board.

lmx2820_config.txt

LMK6B: RE: Request_Details

Nirmal N — Wed, 07 Oct 2026 10:02:41 GMT

Part Number: LMK6B

Hi Request

kindly provide me datasheet and pin 1 orienatation

LMK6B

BQ32000: Reset

Jeff YANG — Wed, 07 Oct 2026 06:05:36 GMT

Part Number: BQ32000

Hi team,

Could you provide information regarding the reset behavior of the BQ32000 during power-up? Specifically, we are looking for details on how the hardware reset operates on this IC, and if there are any critical timing requirements or sequences we need to be aware of. thanks!

Jeff

LMX1205: Download the latest version of TICSPRO-SW (Version 1.7.10.1, released on Oct 17, 2025),

user4779049 — Wed, 07 Oct 2026 01:29:56 GMT

Part Number: LMX1205
Other Parts Discussed in Thread: TICSPRO-SW

Hi Team,

Could you please advise how I can resolve the following issue?

When I tried to download the latest version of TICSPRO-SW (Version 1.7.10.1, released on Oct 17, 2025), the following error message was displayed:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Bad Request

Your browser sent a request that this server could not understand.

Size of a request header field exceeds server limit.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Could you please let me know how to resolve this issue?

Best regards,

Kikuo Mita

AM62P: DDR configuration of 4 GB RAM with TI AM62P5

Roshan Mohammed — Tue, 06 Oct 2026 12:30:21 GMT

Part Number: AM62P

Hi,

I have generated the DDR file for the 4GB Micron MT53E1G32D2FW-046 AAT:C. PFA file.
I choose the 8GB RAM as the reference design and reduced the number of Rank to 1 to change to 4 GB and generated the DDR configuration. Please find the below

I changed the dts file to the below:

memory@80000000 {
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
device_type = "memory";
bootph-pre-ram;
};

After flashing, it started booting and the bdinfo is below:
=> bdinfo
boot_params = 0x0000000000000000
DRAM bank = 0x0000000000000000
-> start = 0x0000000080000000
-> size = 0x0000000080000000
DRAM bank = 0x0000000000000001
-> start = 0x0000000880000000
-> size = 0x0000000080000000
flashstart = 0x0000000000000000
flashsize = 0x0000000000000000
flashoffset = 0x0000000000000000
baudrate = 115200 bps
relocaddr = 0x00000000ffe75000
reloc off = 0x000000007f675000
Build = 64-bit
current eth = ethernet@8000000port@1
ethaddr = 44:88:be:dd:e2:77
IP addr = <NULL>
fdt_blob = 0x00000000f7e3fcf0
multi_dtb_fit= 0x0000000000000000
lmb_dump_all:
memory.count = 0x2
memory[0] [0x80000000-0xffffffff], 0x80000000 bytes, flags: none
memory[1] [0x880000000-0x8ffffffff], 0x80000000 bytes, flags: none
reserved.count = 0x5
reserved[0] [0x9b500000-0x9e6fffff], 0x3200000 bytes, flags: no-map
reserved[1] [0x9e780000-0x9fffffff], 0x1880000 bytes, flags: no-map
reserved[2] [0xf6e0d000-0xf6e3dfff], 0x31000 bytes, flags: no-notify, no-overwrite
reserved[3] [0xf6e3eff0-0xffffffff], 0x91c1010 bytes, flags: no-overwrite
reserved[4] [0x880000000-0x8ffffffff], 0x80000000 bytes, flags: no-overwrite
devicetree = separate
serial addr = 0x0000000002800000
width = 0x0000000000000000
shift = 0x0000000000000002
offset = 0x0000000000000000
clock = 0x0000000002dc6c00
arch_number = 0x0000000000000000
TLB addr = 0x00000000ffff0000
irq_sp = 0x00000000f7e3eff0
sp start = 0x00000000f7e3eff0
Early malloc usage: 3b48 / 8000

I have enabled the mtest and done the memory test by using the below commands.

mtest commands are below:

mtest 0x82000000 0x9b000000 0 1
mtest 0xa0000000 0xf6000000 0 1
mtest 0x880000000 0x8ffffff00 0 1

Everything passed, Could you please verify this changes are correct and valid?

Is there any changes to be done in any of the steps which I followed

Regards

Roshan

LMX2694-EP: LMX2694-EP RFOUTB_P amplitude variation between power cycles (from 400 mVpp to 480 mVpp)

Kobayashi Toshio — Tue, 06 Oct 2026 10:25:50 GMT

Part Number: LMX2694-EP

Hello,

I have a question regarding RFOUTB_P output amplitude variation on the LMX2694-EP.

Configuration

- LMX2694-EP
- RFOUTB configured according to Section 8.1.4.1, “Resistor Pullup,” of the datasheet
- RFOUTB pulled up to +3.3 V through a 50-ohm resistor
- Single-ended operation
- RFOUTB_P used as the output after AC coupling
- RFOUTB_N AC-coupled and terminated with 50 ohm
- R45 (OUTB_PWR) = 0x0A
- Input clock = 155.52 MHz
- Output clock = 1244.16 MHz
- Oscilloscope input impedance = 50 ohm
- Ambient temperature ≈ 25°C
- PLL lock confirmed before each measurement

Observation

The RFOUTB_P output is a square wave.

The amplitude is typically about 440 mVpp, measured as the voltage difference between the logic-high and logic-low levels using a 50-ohm-terminated oscilloscope.

The measurement is performed at the end of an approximately 1 m coaxial cable connected to the RFOUTB_P output.

However, after power-up, the measured amplitude sometimes varies from approximately 400 mVpp to 480 mVpp, even though the register settings and operating conditions remain unchanged.

The output frequency remains correct at 1244.16 MHz, and PLL lock is always achieved.

This variation is mainly observed after the device has been powered off for an extended period, such as overnight.

When the device is power-cycled after only a few minutes, the amplitude is generally very repeatable, and little variation is observed.

Questions

Is a startup-to-startup amplitude variation from approximately 400 mVpp to 480 mVpp expected in this configuration?

Could this behavior be related to internal calibration, startup conditions, or temperature dependence, even though PLL lock and the output frequency remain normal?

What RFOUTB_P amplitude is typically expected with OUTB_PWR = 0x0A?

Is there a recommended method, setting, or procedure to improve amplitude consistency across power cycles?

We are currently evaluating a downstream clock receiver in our application and would like to understand whether this level of amplitude variation is within the expected characteristics of the device.

Thank you for your support.

Best regards,

LMK04828: PLL1 gets unlocked at higher temperature >52°C

sarojini ravi — Tue, 06 Oct 2026 09:12:21 GMT

Part Number: LMK04828

Hi Team,

We are using LMK04828 chip in dual PLL mode with 25MHz TCXO to CLKIN0 path
and 100MHz VCXO (CVHD-950X-100.000) to OSCIN.
If the LMK is powered on while it is cold it locks instantly and maintains lock above 55°C.
When configured at 52°C PLL1 gets unlocked.Loop filter components connected from CPOUT1 to Volt control pin of VCXO
were verified for any degradation of value as the board testing is done since 4 years.
New LMK chip was replaced in the board then also the same issue persists.
We had a freshly assembled board which had only one difference from issue board that is the CPOUT1 voltage which was 1.78V where as issue board had 2.18V.
Upon looking into the query already raised similar to the issue (refer below link),CLKin_OVERRIDE bit was set to 1 and the issue was solved.
Link:https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1035219/lmk04828-pll1-not-locking-at-package-temp-above-36-c-pll1_dld-oscillates

Inspite of setting Pin select mode to CLKIN0 in the configuration,why should we set this override pin.
Kindly clarify the purpose to set this bit.
Is there any other hardware changes that can be done to solve this issue.

Regards
Sarojini R

LMK04610: oscillator for the LMK04610 CLKin

Satoshi Ishizaki — Tue, 06 Oct 2026 08:26:42 GMT

Part Number: LMK04610
Other Parts Discussed in Thread: LMX2820

hello

I have a question concerning the input clock for the LMK04610.

Please provide the recommended specifications for the oscillator in the following configuration:
1.Phase jitter
2.Rise/fall time
3.recommended to use an oscillator with an integrated PLL or one without?

Oscillator(100 MHz LVPECL) -> LMK04610 CLKin -> LMK04610 CLKout -> LMX2820 OSCin -> LMX2820 RFout -> 10.4 GHz

Satoshi .I

Regards,

LMKDB1202: Is it acceptable to swap P/N on both the clock inputs and the outputs?

David Kim2 — Tue, 06 Oct 2026 04:58:03 GMT

Part Number: LMKDB1202

Hello,

We are using LMKDB1202REY as a 2:2 PCIe reference clock mux, as shown in the attached schematic. In this design, the P/N polarity is swapped at both the inputs and the output:

Inputs: For both input pairs (HOST clock and OSC clock), the "_N" net is connected to the positive input pin (CLKIN0/CLKIN1) and the "_P" net is connected to the negative input pin (CLKINB0/CLKINB1).
Output: The positive output pin is connected to the "PCIE_CLK_N" net and the negative output pin is connected to the "PCIE_CLK_P" net.

As a result, the overall polarity from each clock source to the final PCIE_CLK_P/N nets is preserved.

Questions:

Is it acceptable to swap P/N on both the inputs and the outputs of LMKDB1202 as shown in the schematic?
Does this P/N swap have any impact on device performance (such as additive jitter, skew, or mux switching behavior) or on PCIe reference clock compliance?
Are there any restrictions or recommendations regarding clock polarity for this device, for example, whether the polarity must be preserved end-to-end?

Thank you for your help.

LMK01801BEVAL: Having Trouble with Signal

Qi Liu — Mon, 05 Oct 2026 01:49:02 GMT

Part Number: LMK01801BEVAL

Hi, Ive got this board and I'm just having trouble downsampling my 1 ghz sinusodal (+-400mv) signal going into Clk in 1 to any output on clk out 12 (attempting at 10MHZ). Im wondering if therees any specifications that I am missing. When I have the EN PN cntr in and everythign set to U wire I do get a TTL signal but one that is not correct. When I pull it i get no output and continue to get no output after ptogramming

Best Regards,

Jeremy

LMH1982: LMH1982 reset recovery time

Tetsuo Takada — Fri, 02 Oct 2026 05:30:30 GMT

Part Number: LMH1982

How much wait time is required between deasserting the LMH1982 reset and starting the I2C configuration?

LMX2572LP: Oscin Configuration

Peter heng — Fri, 02 Oct 2026 03:58:31 GMT

Part Number: LMX2572LP

hello,i found the reference circuit of the LMX2572LP from the EVM schematic. i plan to use cmos oscillator SXO32C3B481-100.000M(Suntsu) parts. therefore i would like to know do i need to have R35=51ohm connected before the oscillator as shown below.

Pls feel free to provide any other alternative Oscin type with better performance.

Thank you.

LMK1D1208EVM: Proper input and output terminations of LMK1D1204 with single-ended sine wave input

Noman Paracha — Fri, 02 Oct 2026 03:18:51 GMT

Part Number: LMK1D1208EVM
Other Parts Discussed in Thread: LMX2592, LMK1D1204, LMK1D1208

Hi,

I am using LMK1D1204 (Vcc = 3.3V) to convert a single-ended 10 MHz sine wave from a signal generator and produce four LVDS outputs that are fed to OSCin pins of four LMX2592 synthesizer ICs. Per suggestion in LMK1D1208EVM user guide, I made the following modifications on the input side:

The shunt 50 ohms near J3 connector was not mentioned in the user guide, I added it there so I can get the correct bias voltage at the unused input pins. After this addition, I measure 1.65 V on + and - pins of IN0 input, which I believe is correct. Do these changes look correct?

On the output side, i made the following edits so I can connect it to the OSCin+/- pins of LMX2592.

The reason for removing the AC coupling caps (C12 and C14) is that there are AC coupling caps close to LMX2592 OSCin +/- of its eval board. Is this the right thing to do and does this setup look correct to you?

The reason, I am asking all these questions is that I am getting spurs at 6KHz offset at the output of the synthesizer that were not there when I use the on-board TCXO on LMX2592 eval board. See pictures below

Can you help me solve this problem? I have really been strugling with it for the last two weeks and any help will be greatly appreciated.

Thanks,

Noman

LMX2820: Phase noise Degradation when sharing a SPI configuration bus

John Tauch — Thu, 01 Oct 2026 19:38:30 GMT

Part Number: LMX2820

Hello,

I would like to know if the phase noise degradation during SPI bus sharing still applies to the current versions of the LMX2820?

We found a comment about this issue in the following forum post:

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1025886/lmx2820-spi-protocol-details-needed

We were considering sharing this SPI interface with several devices, and this comment is concerning. Has the degradation been quatified? or perhaps it has been fixed in the current versions of the part.

Thanks,

John Tauch

LMX2624-SP: "Call TI" in LMX2624-SP spec

KAtia Araya — Thu, 01 Oct 2026 16:41:03 GMT

Part Number: LMX2624-SP

Looking for information that is missing from LMX2624-SP specification. Spec says to "Call TI," but customer service center is under construction and I cannot reach them. I'm looking for the following information:

MSL rating
Max lead temperature
Peak reflow
Manual solder or mass reflow? Heat sensitive?
Is the package hermetic? Compatible with water soluble flux and aqueous cleaning?

BQ4802LY: Questions on BVF Timing and Crystal Accuracy of BQ4802LY

Ryu Yamashita — Thu, 01 Oct 2026 14:46:02 GMT

Part Number: BQ4802LY

Hi team,

We are using BQ4802LYPW with a 32.768kHz crystal (NX3215SE-32.768K-STD-MUA-19, CL=6pF).

We have two questions.

RTC accuracy The RTC is running approximately 99ppm fast. The crystal specification is within the recommended load capacitance range and follows the datasheet connection method.

Does TI have any layout recommendations beyond the datasheet?
Could guard ground around the crystal affect oscillator frequency?
Are there any known oscillator sensitivity parameters for BQ4802LY?

Battery Valid Flag (BVF) We would like to detect battery degradation through BVF.

At what timing is BVF evaluated?
Is BVF checked continuously or only during power-up events?
What is the BVF threshold voltage for the 3-V battery input?
Is there any timing chart showing BVF update behavior versus battery voltage and VCC transitions?

Best Regards,
Ryu.

LMK03318: LMK03318RHSTT1 is this part available and active? if not do we have alternates?

Ha C — Thu, 01 Oct 2026 09:30:25 GMT

Part Number: LMK03318

LMK03318RHSTT1 is this part available and active? if not do we have alternates?

LMKDB1202: LMKDB1202 — does it behave as LMKDB1204 with all registers fixed at reset/default values?

David Kim2 — Thu, 01 Oct 2026 07:43:58 GMT

Part Number: LMKDB1202
Other Parts Discussed in Thread: LMKDB1208, LMKDB1204,

Hello,

We are evaluating LMKDB1202REY and have a question about how it relates to LMKDB1204/LMKDB1208 within the same family.

From the datasheet, we understand:

LMKDB1202 does not have SMB_DATA/SMB_CLK pins (Table 5-3), so it has no SMBus register access.
LMKDB1204 and LMKDB1208 do support SMBus and have documented register maps (Section 9.1 and 9.2) for settings such as input AC/DC coupling, input termination enable, output amplitude, and slew rate selection.
Figure 8-2 "Functional Block Diagram" is shared/labeled for both LMKDB1204 and LMKDB1202, suggesting they share the same internal architecture.
LMKDB1202 has no pins that expose these settings (AC/DC coupling, input termination, output amplitude, slew rate) as pin-strap options either.

Question:

Given the above, is it correct to assume that LMKDB1202 operates internally as if all the same registers listed in the LMKDB1204 register map (Section 9.1) are permanently fixed at their documented reset/default values (e.g., input termination disabled, AC-coupling disabled, default output amplitude, default slew rate option)?

If LMKDB1202 does not share the exact same register reset values as LMKDB1204, could you clarify what the actual default configuration is for LMKDB1202 specifically?

Thank you for your help.

LMK00334-Q1: Recommendation specs on external clock

Shotaro Sakai — Thu, 01 Oct 2026 01:13:04 GMT

Part Number: LMK00334-Q1

Hello team,

Can you tell me recommendation specs on external clock?

Output format of the clock
Frequency
Tolerance (including temperature change and aging change)
If there are any other additional items to be noted

Best regards,

Shotaro