Clock & timing forum - Recent Threads

LMK04828: Technical Inquiry

TI-CSC — Wed, 08 Jul 2026 09:36:20 GMT

Part Number: LMK04828

Hello E2E Experts,

Is it possible to use this part given the conditions below?

Generate a stable 1Hz signal from a 10MHz reference.
Automatically switch between external and internal clock sources.
Achieve high precision, potentially down to the 20 ppb level.
Be reliable enough for practical hardware implementation.

Any reference the customer can use?

Regards,

TICSC

LMK5B33216: LMK5B33216 Clock Tree Design - EVM Files Download Request

sun johnny — Wed, 08 Jul 2026 08:34:28 GMT

Part Number: LMK5B33216
Other Parts Discussed in Thread: TICSPRO-SW

Dear TI Support Team,

I am currently evaluating the LMK5B33216 device for a new clock tree design in our communication system project.

I am trying to download the following resources from the TI website for design evaluation and schematic review:
- LMK5B33216EVM design files (including schematic, PCB layout, and Gerber files)
- Latest datasheet and application notes
- Reference design for 1PPS input/output application

However, I encountered the following error message when attempting the download:
"We are unable to approve your download at this time."

My myTI account information is as follows:
- Name: [Your Name]
- Email: [Your Email Address, preferably company email]
- Company: [Your Company Name]
- Country: [Your Country]

Our application requires the following key features of the LMK5B33216:
- 1Hz (1PPS) input and output support
- 10MHz reference input with automatic hitless switching to internal XO
- Ultra-low jitter BAW APLL performance

Could you please help me gain access to these design files? I would also appreciate any additional reference designs or application notes related to this device.

Please let me know if you need any additional information.

Thank you for your support.

Best regards,

LMX2594: can we configure LMX2594 differential RF output power is 10dBm?

Jifei Chen — Wed, 08 Jul 2026 08:13:40 GMT

Part Number: LMX2594

Hello!

Differential RF output frequency is 915MHz, the RF output RFoutAM/RFoutAP are pulluped 50R connected to VccRF.

Can we configure LMX2594 differential RF 915MHz output power is 10dBm?If it is true, how to set the related registers? If don't get the 10dBm, what is the maximum power under above RFout HW setting with resistor 50R pullup to Vcc?

If I want to have 915MHz maximum power output, how can we design the circuits for the RFoutAM/RFoutAP?

thanks!

Chen

LMC555: Qualifying the part for our application

Pitariu Serban — Wed, 08 Jul 2026 07:11:41 GMT

Part Number: LMC555

Hello TI team,

My name is Pitariu Serban and I'm a component engineer for SIMEA Sibiu SRL(part of SIEMENS AG).

Our R&D department would like to qualify the LMC555MMX manufactured in Richardson - RFAB location.

Could you please provide us with 20 samples of the specified part number which are manufactured in the RFAB location?

Delivery adress will be:

SIMEA SIBIU S.R.L.
Strada Florian Rieger Nr. 4
550018 Sibiu, Romania
Phone: +40 369130601
Fax.: +40 369130678

Contact person:
Pitariu Serban
+40744788893

Thanks in advance for your support.

With best regards,

Serban Pitariu
SIMEA SIBIU S.R.L.
DI PA GFN SQM SQE-EL
Strada Florian Rieger Nr. 4
550018 Sibiu, Romania
Phone: +40 369130601
Fax.: +40 369130678
mailto:serban.pitariu@siemens.com

TXS0102-Q1: TXS0102-Q1 : Input transition rise and fall time

Takuya SAITO — Tue, 07 Jul 2026 06:36:20 GMT

Part Number: TXS0102-Q1
Other Parts Discussed in Thread: LSF0102-Q1

Hi TI Team

I am using this part with 400kHz I2C interface and rise and fall timing failed
Measurement result : Rise time 70ns/V Fall time 40nS/V . Spec : Less than 10ns/V

However, the slave side's specifications(NXP common standard) can be passed because it is 20nS or higher.

Question

I think it would be difficult to satisfy both of these specifications at the same time. Why does this part recommend to use I2C interface?
Could you please tell me how to solve this isseu? Should I change this part to another one (ex,LSF0102-Q1 )?

CDCS501: SSC pin

Yuta Nishie — Tue, 07 Jul 2026 06:11:58 GMT

Part Number: CDCS501

HI,

I found the thread below.

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/959479/cdcs502-ssc_sel0-1-and-fs-pin-handling?tisearch=e2e-sitesearch&keymatch=CDCS502

Would it be acceptable to connect each SSC pin of the CDCS501 directly to either VDD or GND?

I understand that external pull-up or pull-down resistors are not required. Could you please confirm whether my understanding is correct?

Best Regards,

Nishie

LMK6C: LMK6CE02500DDLFR not outputting a clock signal

Jesus Aldaco — Tue, 07 Jul 2026 03:05:23 GMT

Part Number: LMK6C

Hello,

We have an application where we are using the LMK6CE chip to drive a 25MHz clock signal for the ethernet transceiver chip DP83867ERGZT. When probing on the output of the clock we see a constant 1V signal.

We had the OE pin floating and later pulled high (to 1.8V) but in both cases we see the constant 1V signal. What are we doing wrong ? Feel free to reach out direcly on my email for more details.

TPL5111: TPL5111 DONE signal clarification

Alex Forrest — Mon, 06 Jul 2026 20:15:01 GMT

Part Number: TPL5111

If the TPL5111 is active and does not recieve a DONE signal, how long will it stay active? Is it possible to use this IC to keep a circuit off for 2 minutes, and then enable it for 50 ms?

LMK04832EVM: Not able to do Phase Synchronization with Multiple Devices

Mohammad Malmir — Mon, 06 Jul 2026 13:49:55 GMT

Part Number: LMK04832EVM
Other Parts Discussed in Thread: LMK04832,

Hi,

I'm trying to achieve phase synchronization across multiple LMK04832 devices, as described in Phase Synchronization with Multiple Devices and Frequencies (Rev. A)

As a proof of concept, I am building a simple synchronized clock distribution prototype using four LMK04832EVM boards, arranged as shown in the Figure 1.

LMK04832EVM #1 is configured as a fan-out buffer and SYNC retimer (BUFF + SRT). It receives an 80 MHz reference clock (preferably from a VCXO, although another stable source could be used) and distributes this clock to LMK04832EVM #3 and #4. It also receives a SYNC command (currently a single 1 ms pulse generated by a ZedBoard) and distributes it to the CLKin1 of EVMs #2.

LMK04832EVM #2 is configured as a fan-out buffer (BUFF) for the SYNC signal.

LMK04832EVM #3 and #4 are configured as standard clock-generation devices using their PLL and clock distribution functions to generate various output frequencies.

The objective is to generate multiple frequencies (for example, 40 MHz, 400 MHz, 2 MHz, etc.) that are phase-aligned, such that the first output edge of all generated clocks across all PLL-DIST devices is coincident, as illustrated in the synchronization example shown in the Figure 2.

I am using TICS Pro to configure and program the evaluation boards. When I issue a SYNC signal, I can observe synchronization between the output clocks within an individual LMK04832EVM. However, I do not see any phase synchronization between outputs generated by different LMK04832EVM boards.

Could you please advise whether my architecture is correct and whether there are any additional configuration requirements, register settings, timing constraints, or SYNC signal considerations needed to achieve deterministic phase alignment across multiple LMK04832 devices?

Thank you for your help.

TLC555: Regarding datasheet Rev.J

Daisuke Higa — Mon, 06 Jul 2026 02:53:07 GMT

Part Number: TLC555

Hi support team all.

I would like to review the details of the changes made in the 2023 PCN; could you please provide the Rev. J datasheet?

Best regards,

TPS3813K33-EP: TPS3813K33QDBVRQ1 statistical data

Marco Knaus — Fri, 03 Jul 2026 12:11:41 GMT

Part Number: TPS3813K33-EP

Hello

We are using the window watchdog mentioned in the title to verify proper operation of our CPU. We have observed a higher number of devices on the lower end of the tolerance band in the recent past. Could TI support our investigations with statistics acquired during the production of this chip? Has there been a silicon revision in the last couple of months or years?

Regards, Marco Knaus

LMK05028: 2-LOOP TCXO-DPLL Mode

Takumi Suzuki1 — Fri, 03 Jul 2026 07:13:00 GMT

Part Number: LMK05028

Hi,

I would like to ask for your assistance with 2 points about clock generation using the LMK05028 as below.

Q1) In 2-Loop TCXO-DPLL mode, when generating a clock, I understand that the output clock ahould be dependent on the TCXO's frequency deviation. However, even when LOS_TXCO and LOS_FDET_TCXO are not occurring, the output clock is dependent on the XO's frequency deviation.

* This appears to be operating as if the TXCO-DPLL is unlocked and the clock is being generated only by the APLL.

The detected alarms are :

- LOPL_DPLLx

- LOFL_DPLLx

- HLDOVRx

I understand that all of these represent alarm states for the REF-DPLL. Are ther any settings I should be aware of?

Q2) Also, the register types for LOS_TXCO and LOS_FDET_TCXO are read. When an alarm is detected, does the detection state persist until a read access occurs?

* If it was not a latch hold, does that mean that the TCXO alarm was not detected at the time of the read access?

Is that correct?

Many thanks for your strong support.

Best Regards,

Takumi

CDCLVP111-SP: CDCLVP111 CLK_SEL Pulldown Resistor Needed?

William Cai — Thu, 02 Jul 2026 19:08:45 GMT

Part Number: CDCLVP111-SP

Hello,

Is a pulldown resistor required to pull the CLK_SEL pin to GND? If so, what is an appropriate value? I didn't see any mention of a pulldown in the eval board design and the datasheet, but just wanted to make sure.

Thanks,

Will

CDCLVP111-SP: test

Mark Caskey — Thu, 02 Jul 2026 17:04:21 GMT

Part Number: CDCLVP111-SP

test

CDCLVC1103: Clock buffer for 10pF load

Hiromu Susami — Thu, 02 Jul 2026 11:11:12 GMT

Part Number: CDCLVC1103
Other Parts Discussed in Thread: LMK00105

Hi team,

We plan to supply clock to IGLOO2. The input buffer of IGLOO2 is 10pF(max).

Previous thread shows CDCLVC110x is designed for 8pF(max) application. Can you recommend a clock buffer with higher drive capability? Let me know if you need more requirements.

CDCLVC1103 Clock Buffer - Clock & timing forum - Clock & timing - TI E2E support forums

Regards,
Hiromu

LMK5B33216: TI solution for Skyworks SI5361B-A17807-GM

Jenny Chen — Thu, 02 Jul 2026 10:13:25 GMT

Part Number: LMK5B33216
Other Parts Discussed in Thread: LMK5B33414,

Hi team,

Plesae help to recommend TI solution for Skyworks SI5361B-A17807-GM.

Thanks!

Jenny

LMX2572LP: LMX2572 – occasional missing LD rising edge during hopping

Mark — Thu, 02 Jul 2026 10:11:00 GMT

Part Number: LMX2572LP
Other Parts Discussed in Thread: LMX2572

Hi,

We use LMX2572 in full‑assist mode with MUXout = lock detect. We hop through N frequencies (e.g., N=201). We always wait for LD high before starting the next hop. Normally we capture N rising edges on LD. Occasionally, we capture only N‑1 edges – one hop seems to produce no low‑to‑high transition.

Configuration:

fpd = 100 MHz
LD_DLY = 300 (which gives 12 µs delay)
LD_TYPE = 1 (VCO calibration + Vtune check)
Dwell time after each lock = 10 µs

Questions:

Is it possible that during a hop the LD pin stays high (never goes low) and the device still reports lock?
What is the minimum guaranteed low‑pulse width of LD during a hop?
Do LD_TYPE or LD_DLY affect this low‑pulse behavior?

We want to confirm whether this could be a chip‑internal issue before debugging our FPGA sampling. Thanks.

LMK5B33216: Inquiry regarding offline pre-programming (Socket) and EEPROM/NVM burning requirements for mass production

Daniel Cheng1 — Thu, 02 Jul 2026 01:52:13 GMT

Part Number: LMK5B33216

Hi TI Team,

We are currently evaluating the LMK5B33216 for a new project. To optimize our mass production line and SMT process efficiency, we would like to pre-program the configuration profile (generated from TICS Pro) into the chip's internal EEPROM prior to SMT board mounting.

Regarding this offline pre-programming approach, we have the following two questions:

Official Socket Support: Does TI offer or recommend an official external programming socket/adapter for the LMK5B33216 (64-pin QFN package)? If yes, could you please provide the corresponding part number or orderable model for the socket wrapper/adapter?
Pre-Programming & NVM Requirements: When programming the internal EEPROM offline before SMT, are there any specific hardware or software constraints we need to follow? Specifically, please advise on:
- VDD Supply Voltage: Is there a specific voltage restriction or higher programming voltage requirement (e.g., for NVM programming) compared to normal operation?
- Minimum Pin Connections: Which hardware pins must be connected to the programmer interface (e.g., VDD, GND, I2C/SPI lines, RESET, or specific control pins)?
- Programming Sequence/Registers: Are there any specific register unlock sequences, non-volatile memory counter (NVMCNT) handling, or CRC verification flows that must be executed to successfully lock the configuration into the EEPROM?

Any documentation, application notes, or guidelines regarding off-board programming for this device family would be highly appreciated.

Thank you for your support.

Best regards,

Daniel

TLC555: RMA-2026-09113

Ruby Deanda — Wed, 01 Jul 2026 22:03:01 GMT

Part Number: TLC555

Per customer, these parts are currently failing on the line. Parts believed to be counterfeit.

CDCE6214-Q1: Prerequisite for EEPROM programming only with PDN

Heike Reurik — Wed, 01 Jul 2026 14:17:54 GMT

Part Number: CDCE6214-Q1
Other Parts Discussed in Thread: CDCI6214, CDCE6214,

I want to replace the CDCI6214 with the CDCE6214. According to the datasheet it is required to repowering all the supplies to bring the device into a known state. Our actual design with the CDCI6214 just uses the PDN (RESETN) pin with active power supply with no problems during programming ( Altough the datasheet of the CDCI6214 also requires shutting down the supply, but we did not implement that erroneously)
Are the steps 1) and 4) realy necessary for the CDCE? If so, a revision of our board would be necessary.
Thank you for your support.

CDCVF25081: Feedback Input Non-monotonicity

Jennifer H — Wed, 01 Jul 2026 14:16:20 GMT

Part Number: CDCVF25081

Hello,

In an application where an unused output is connected to the feedback pin (pin 16), will non-monotonicity at the feedback pin have an impact on the other outputs?

Thanks!

LMK60A0-148M: LMK60A0-148M35SIAT construction and material composition

Chee Xiang Lee — Wed, 01 Jul 2026 03:13:39 GMT

Part Number: LMK60A0-148M

HI TI Team,

Could you please provide the construction and material composition of the MPN below for China customs registration?

TI MPN: LMK60A0-148M35SIAT

LMK04832: Firmware simulation model

Samuel Li — Tue, 30 Jun 2026 23:03:04 GMT

Part Number: LMK04832

Is there a Verilog/VHDL simulation model of the LMK04832 where you can send the SPI signals to program the registers and see the clock waveform coming out of the model?

Thank you!

BQ32000: When BQ32000 with high Rs, the CL choose

neko lin — Tue, 30 Jun 2026 13:43:34 GMT

Part Number: BQ32000

In the bq32000 datasheet, the crystal series resistance (Rs) is specified as 70k ohm, and no external load capacitors (CL) are required. However, if we have to use a crystal with Rs = 85k ohm, would you recommend adding CL? If so, what capacitance value would you suggest? 5pF? 10pF?

LMK04828-EP: Default Output frequencies of LMK04828 during Board Bring-Up

GAURAV UPADHYAY — Tue, 30 Jun 2026 12:08:22 GMT

Part Number: LMK04828-EP
Other Parts Discussed in Thread: LMK04828

Dear Sir/Ma'am,

I have a few queries regarding the LMK04828:

During board bring-up, when only a 10 MHz input reference is applied and a 160 MHz clock is present, what are the default output frequencies of the LMK04828?
Is it necessary to add a level translator on the output clock signals? If not, could you please explain the reason why a level translator is not required?
Which pins of the LMK04828 should be supplied with 3.3 V, and which pins should be supplied with 1.8 V?

I would appreciate your guidance on the above points.

Best Regards,

Gaurav