Clock & timing forum - Recent Threads

TPS3813K33-EP: TPS3813K33QDBVRQ1 statistical data

Marco Knaus — Fri, 03 Jul 2026 12:11:41 GMT

Hello

We are using the window watchdog mentioned in the title to verify proper operation of our CPU. We have observed a higher number of devices on the lower end of the tolerance band in the recent past. Could TI support our investigations with statistics acquired during the production of this chip? Has there been a silicon revision in the last couple of months or years?

Regards, Marco Knaus

LMK05028: 2-LOOP TCXO-DPLL Mode

Takumi Suzuki1 — Fri, 03 Jul 2026 07:13:00 GMT

Part Number: LMK05028

Hi,

I would like to ask for your assistance with 2 points about clock generation using the LMK05028 as below.

Q1) In 2-Loop TCXO-DPLL mode, when generating a clock, I understand that the output clock ahould be dependent on the TCXO's frequency deviation. However, even when LOS_TXCO and LOS_FDET_TCXO are not occurring, the output clock is dependent on the XO's frequency deviation.

* This appears to be operating as if the TXCO-DPLL is unlocked and the clock is being generated only by the APLL.

The detected alarms are :

- LOPL_DPLLx

- LOFL_DPLLx

- HLDOVRx

I understand that all of these represent alarm states for the REF-DPLL. Are ther any settings I should be aware of?

Q2) Also, the register types for LOS_TXCO and LOS_FDET_TCXO are read. When an alarm is detected, does the detection state persist until a read access occurs?

* If it was not a latch hold, does that mean that the TCXO alarm was not detected at the time of the read access?

Is that correct?

Many thanks for your strong support.

Best Regards,

Takumi

CDCLVP111-SP: CDCLVP111 CLK_SEL Pulldown Resistor Needed?

William Cai — Thu, 02 Jul 2026 19:08:45 GMT

Part Number: CDCLVP111-SP

Hello,

Is a pulldown resistor required to pull the CLK_SEL pin to GND? If so, what is an appropriate value? I didn't see any mention of a pulldown in the eval board design and the datasheet, but just wanted to make sure.

Thanks,

Will

CDCLVP111-SP: test

Mark Caskey — Thu, 02 Jul 2026 17:04:21 GMT

Part Number: CDCLVP111-SP

test

CDCLVC1103: Clock buffer for 10pF load

Hiromu Susami — Thu, 02 Jul 2026 11:11:12 GMT

Part Number: CDCLVC1103
Other Parts Discussed in Thread: LMK00105

Hi team,

We plan to supply clock to IGLOO2. The input buffer of IGLOO2 is 10pF(max).

Previous thread shows CDCLVC110x is designed for 8pF(max) application. Can you recommend a clock buffer with higher drive capability? Let me know if you need more requirements.

CDCLVC1103 Clock Buffer - Clock & timing forum - Clock & timing - TI E2E support forums

Regards,
Hiromu

LMK5B33216: TI solution for Skyworks SI5361B-A17807-GM

Jenny Chen — Thu, 02 Jul 2026 10:13:25 GMT

Part Number: LMK5B33216
Other Parts Discussed in Thread: LMK5B33414,

Hi team,

Plesae help to recommend TI solution for Skyworks SI5361B-A17807-GM.

Thanks!

Jenny

LMX2572LP: LMX2572 – occasional missing LD rising edge during hopping

Mark — Thu, 02 Jul 2026 10:11:00 GMT

Part Number: LMX2572LP
Other Parts Discussed in Thread: LMX2572

Hi,

We use LMX2572 in full‑assist mode with MUXout = lock detect. We hop through N frequencies (e.g., N=201). We always wait for LD high before starting the next hop. Normally we capture N rising edges on LD. Occasionally, we capture only N‑1 edges – one hop seems to produce no low‑to‑high transition.

Configuration:

fpd = 100 MHz
LD_DLY = 300 (which gives 12 µs delay)
LD_TYPE = 1 (VCO calibration + Vtune check)
Dwell time after each lock = 10 µs

Questions:

Is it possible that during a hop the LD pin stays high (never goes low) and the device still reports lock?
What is the minimum guaranteed low‑pulse width of LD during a hop?
Do LD_TYPE or LD_DLY affect this low‑pulse behavior?

We want to confirm whether this could be a chip‑internal issue before debugging our FPGA sampling. Thanks.

LMK5B33216: Inquiry regarding offline pre-programming (Socket) and EEPROM/NVM burning requirements for mass production

Daniel Cheng1 — Thu, 02 Jul 2026 01:52:13 GMT

Part Number: LMK5B33216

Hi TI Team,

We are currently evaluating the LMK5B33216 for a new project. To optimize our mass production line and SMT process efficiency, we would like to pre-program the configuration profile (generated from TICS Pro) into the chip's internal EEPROM prior to SMT board mounting.

Regarding this offline pre-programming approach, we have the following two questions:

Official Socket Support: Does TI offer or recommend an official external programming socket/adapter for the LMK5B33216 (64-pin QFN package)? If yes, could you please provide the corresponding part number or orderable model for the socket wrapper/adapter?
Pre-Programming & NVM Requirements: When programming the internal EEPROM offline before SMT, are there any specific hardware or software constraints we need to follow? Specifically, please advise on:
- VDD Supply Voltage: Is there a specific voltage restriction or higher programming voltage requirement (e.g., for NVM programming) compared to normal operation?
- Minimum Pin Connections: Which hardware pins must be connected to the programmer interface (e.g., VDD, GND, I2C/SPI lines, RESET, or specific control pins)?
- Programming Sequence/Registers: Are there any specific register unlock sequences, non-volatile memory counter (NVMCNT) handling, or CRC verification flows that must be executed to successfully lock the configuration into the EEPROM?

Any documentation, application notes, or guidelines regarding off-board programming for this device family would be highly appreciated.

Thank you for your support.

Best regards,

Daniel

TLC555: RMA-2026-09113

Ruby Deanda — Wed, 01 Jul 2026 22:03:01 GMT

Part Number: TLC555

Per customer, these parts are currently failing on the line. Parts believed to be counterfeit.

CDCE6214-Q1: Prerequisite for EEPROM programming only with PDN

Heike Reurik — Wed, 01 Jul 2026 14:17:54 GMT

Part Number: CDCE6214-Q1
Other Parts Discussed in Thread: CDCI6214, CDCE6214,

I want to replace the CDCI6214 with the CDCE6214. According to the datasheet it is required to repowering all the supplies to bring the device into a known state. Our actual design with the CDCI6214 just uses the PDN (RESETN) pin with active power supply with no problems during programming ( Altough the datasheet of the CDCI6214 also requires shutting down the supply, but we did not implement that erroneously)
Are the steps 1) and 4) realy necessary for the CDCE? If so, a revision of our board would be necessary.
Thank you for your support.

CDCVF25081: Feedback Input Non-monotonicity

Jennifer H — Wed, 01 Jul 2026 14:16:20 GMT

Part Number: CDCVF25081

Hello,

In an application where an unused output is connected to the feedback pin (pin 16), will non-monotonicity at the feedback pin have an impact on the other outputs?

Thanks!

LMK60A0-148M: LMK60A0-148M35SIAT construction and material composition

Chee Xiang Lee — Wed, 01 Jul 2026 03:13:39 GMT

Part Number: LMK60A0-148M

HI TI Team,

Could you please provide the construction and material composition of the MPN below for China customs registration?

TI MPN: LMK60A0-148M35SIAT

LMK04832: Firmware simulation model

Samuel Li — Tue, 30 Jun 2026 23:03:04 GMT

Part Number: LMK04832

Is there a Verilog/VHDL simulation model of the LMK04832 where you can send the SPI signals to program the registers and see the clock waveform coming out of the model?

Thank you!

BQ32000: When BQ32000 with high Rs, the CL choose

neko lin — Tue, 30 Jun 2026 13:43:34 GMT

Part Number: BQ32000

In the bq32000 datasheet, the crystal series resistance (Rs) is specified as 70k ohm, and no external load capacitors (CL) are required. However, if we have to use a crystal with Rs = 85k ohm, would you recommend adding CL? If so, what capacitance value would you suggest? 5pF? 10pF?

LMK04828-EP: Default Output frequencies of LMK04828 during Board Bring-Up

GAURAV UPADHYAY — Tue, 30 Jun 2026 12:08:22 GMT

Part Number: LMK04828-EP
Other Parts Discussed in Thread: LMK04828

Dear Sir/Ma'am,

I have a few queries regarding the LMK04828:

During board bring-up, when only a 10 MHz input reference is applied and a 160 MHz clock is present, what are the default output frequencies of the LMK04828?
Is it necessary to add a level translator on the output clock signals? If not, could you please explain the reason why a level translator is not required?
Which pins of the LMK04828 should be supplied with 3.3 V, and which pins should be supplied with 1.8 V?

I would appreciate your guidance on the above points.

Best Regards,

Gaurav

LMK1D1204: How to couple LMK1D1204 to clipped sine VCXO

Miguel S — Tue, 30 Jun 2026 11:25:58 GMT

Part Number: LMK1D1204

Hi,

I am considering to use LMK1D1204 as a buffer for a 0.8Vpp clipped sine generated from a VCXO:

How should I couple this signal to LMK1D1204? How should I bias both PRIREF_P and PRIREF_N?

Thanks,

Miguel

BQ32002: Crystal resonator selection

hiroshi.yamada — Tue, 30 Jun 2026 05:26:31 GMT

Part Number: BQ32002

We are currently using the NDK crystal resonator NX3215SE-32.768K-STD-MUA-17.

According to the results of a matching test conducted by the manufacturer (NDK), the required negative resistance is 180 kohm, whereas our circuit only achieves approximately 40 kohm, which is insufficient to ensure proper operation.

We are using 18 pF external load capacitors for the crystal. Even when these capacitors are removed, the negative resistance only increases to about 130 kohm, which is still below the required level.

Do you have any recommended crystal resonators that are better matched to the BQ32002D?

Currently, the operating conditions are as follows:

Drive level: 0.1 µW
Frequency deviation: −89 dF/F (×10⁻⁶)

LMK04828-EP: Review and suggest correction for Hardware design

GAURAV UPADHYAY — Tue, 30 Jun 2026 04:35:10 GMT

Part Number: LMK04828-EP
Other Parts Discussed in Thread: LMK04828, LMX2594

Dear Sir/ Ma'am,

Please reveiw attached schematic of LMK04828 and share your comments to improve my design.

Best Regards,

Gaurav

LMX2572LPEVM: Phase Noise in VCO3

keita matsuzaki — Tue, 30 Jun 2026 02:02:33 GMT

Part Number: LMX2572LPEVM
Other Parts Discussed in Thread: LMX2572LP

I have noticed that the phase noise performance of VCO3 in the LMX2572LP is worse than that of the other VCOs.

Figure 1 shows the phase noise of VCO3 at its upper frequency limit and VCO4 at its lower frequency limit, measured using a signal source analyzer. Figure 2 shows the simulation results at the same frequencies.

In order to focus on the phase noise originating from the VCO, we compared the phase noise at offsets of 1 kHz and above, assuming a loop bandwidth of approximately 1 kHz. As a result, we found that VCO4 achieves performance close to the simulation results, whereas when switching to VCO3, the phase noise at offsets from 10 kHz to 100 kHz deteriorates and deviates significantly from the simulation results.

Could you please explain the possible reasons for this discrepancy?

Could you also please tell me how to resolve this?

LP5815DRLEVM: About Internal oscillator frequency

yuko yamazaki — Tue, 30 Jun 2026 00:17:17 GMT

Part Number: LP5815DRLEVM

Can you tell me about the accuracy of the internal oscillator's frequency?

LMX2594: LOCK STATUS UNSTABLE

Srinadh Moka — Mon, 29 Jun 2026 13:32:59 GMT

Part Number: LMX2594

Hi,

I am configuring the LMX2594 with the XCZU19EG MPSoC. I have verified that during a single configuration cycle, the expected output frequency is 56 MHz, with a 10 MHz reference clock. The register values used for configuration are provided below.

config_reg(112) <= x"700000";

config_reg(111) <= x"6F0000";

config_reg(110) <= x"6E0000";

config_reg(109) <= x"6D0000";

config_reg(108) <= x"6C0000";

config_reg(107) <= x"6B0000";

config_reg(106) <= x"6A0000";

config_reg(105) <= x"690021";

config_reg(104) <= x"680000";

config_reg(103) <= x"670000"; --091604

config_reg(102) <= x"663B00";

config_reg(101) <= x"650011";--0B0018

config_reg(100) <= x"640000";

config_reg(99) <= x"630000";

config_reg(98) <= x"621400";

config_reg(97) <= x"610888";

config_reg(96) <= x"600000";

config_reg(95) <= x"5F0000";

config_reg(94) <= x"5E0000";

config_reg(93) <= x"5D0000";

config_reg(92) <= x"5C0000";

config_reg(91) <= x"5B0000";

config_reg(90) <= x"5A0000";

config_reg(89) <= x"590000";

config_reg(88) <= x"580000";

config_reg(87) <= x"570000";

config_reg(86) <= x"560000";

config_reg(85) <= x"550000";

config_reg(84) <= x"540001";

config_reg(83) <= x"53FFFF";

config_reg(82) <= x"52FFFF";

config_reg(81) <= x"510000";

config_reg(80) <= x"500000";

config_reg(79) <= x"4F0180";

config_reg(78) <= x"4E0003";

config_reg(77) <= x"4D0000";

config_reg(76) <= x"4C000C"; --240219

config_reg(75) <= x"4B0B40";

config_reg(74) <= x"4A0000";

config_reg(73) <= x"49003F";

config_reg(72) <= x"480001";

config_reg(71) <= x"470081";

config_reg(70) <= x"46C350";

config_reg(69) <= x"450000"; --2B0258

config_reg(68) <= x"4403E8";

config_reg(67) <= x"430000";

config_reg(66) <= x"4201F4";

config_reg(65) <= x"410000";

config_reg(64) <= x"401388";

config_reg(63) <= x"3F0000";

config_reg(62) <= x"3E0322";

config_reg(61) <= x"3D00A8";

config_reg(60) <= x"3C0000";

config_reg(59) <= x"3B0001";

config_reg(58) <= x"3A9001";

config_reg(57) <= x"390020";

config_reg(56) <= x"380000";

config_reg(55) <= x"370000";

config_reg(54) <= x"360000";

config_reg(53) <= x"350000";

config_reg(52) <= x"340820";

config_reg(51) <= x"330080";

config_reg(50) <= x"320000";

config_reg(49) <= x"314180";

config_reg(48) <= x"300300";

config_reg(47) <= x"2F0300";

config_reg(46) <= x"2E07FC";

config_reg(45) <= x"2DC0DF";

config_reg(44) <= x"2C1F23";

config_reg(43) <= x"2B9999";

config_reg(42) <= x"2A9999";

config_reg(41) <= x"290000";

config_reg(40) <= x"280000";

config_reg(39) <= x"27FFFF";

config_reg(38) <= x"26FFFF";

config_reg(37) <= x"250404";

config_reg(36) <= x"240219";

config_reg(35) <= x"230004";

config_reg(34) <= x"220000";

config_reg(33) <= x"211E21"; --4F0026

config_reg(32) <= x"200393"; --506666

config_reg(31) <= x"1F43EC"; --

config_reg(30) <= x"1E318C"; --521E00

config_reg(29) <= x"1D318C"; --530000

config_reg(28) <= x"1C0488"; --

config_reg(27) <= x"1B0002"; --55D2FF

config_reg(26) <= x"1A0DB0"; --56FFFF

config_reg(25) <= x"190C2B";

config_reg(24) <= x"18071A";

config_reg(23) <= x"17007C";

config_reg(22) <= x"160001";

config_reg(21) <= x"150401";

config_reg(20) <= x"14E048";

config_reg(19) <= x"1327B7";

config_reg(18) <= x"120064";

config_reg(17) <= x"11012C";

config_reg(16) <= x"100080";

config_reg(15) <= x"0F064F";

config_reg(14) <= x"0E1E70";--620200

config_reg(13) <= x"0D4000";--630000

config_reg(12) <= x"0C5001";

config_reg(11) <= x"0B0018";

config_reg(10) <= x"0A10D8"; --663F80

config_reg(9) <= x"091604"; --670000

config_reg(8) <= x"082000";

config_reg(7) <= x"0740B2";

config_reg(6) <= x"06C802";

config_reg(5) <= x"0500C8";

config_reg(4) <= x"040A43";

config_reg(3) <= x"030642";

config_reg(2) <= x"020500";

config_reg(1) <= x"010808";

config_reg(0) <= x"00241C";

I have observed that the lock status is unstable and the output clock is also sometimes unstable and sometimes stable. What could be the issue—whether it is a register writing delay issue or a hardware issue? For every register write, a delay needs to be included.

Thanks

Srinadh

LMX2572: SYNC and MASH_SEED function

wenhao Huang — Mon, 29 Jun 2026 07:47:04 GMT

Part Number: LMX2572
Other Parts Discussed in Thread: LMX2594,

Hi Teams,

I saw in https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1544486/lmx2594psevm-sync-and-mash_seed-function?tisearch=e2e-sitesearch&keymatch=LMX2820%25252525252525252520SYNC when LMX2594 SYNC is enabled, MASH_SEED will become unstable.

However, when I check the datasheet of LMX2572, the phase adjustment section did not say same thing as which in LMX2594 datasheet. I want to confirm will the LMX2572 have same problem or not. Since LMX2572 have the includeddivide too, I am afraid it is the same as LMX2594.

Best Regards

LMK04828-EP: Clock selection logic for LMK04828

GAURAV UPADHYAY — Fri, 26 Jun 2026 12:28:06 GMT

Part Number: LMK04828-EP

Dear Sir/Ma'am,

What is the recommended approach for implementing the clock selection logic when one clock is used as the primary source and the other as a backup—hardware-based or software-based?

Best Regards,

Gaurav

LMK04828-EP: Electrical Characterstics of Output Configuration of DCLK and SDCLK

Gireesh Kumar — Fri, 26 Jun 2026 09:36:44 GMT

Part Number: LMK04828-EP

Hi TI team,

For the below two cases 1.6Vpp LVPECL and 2Vpp LVPECL Clock Outputs,Can you provide the mathematical explanation of how VOH and VOL values for the respective test cases with derivation.

Thanks & Rewards

Gireesh

LMK00105: Driving four Clipped Sinewaves from LMK00105

Avinash Koushik — Fri, 26 Jun 2026 04:09:59 GMT

Part Number: LMK00105

Hi,

We want to use LMK00105 clock driver IC to drive Clipped SIne wave from a ECS-TXO-20CSMV TCXO to four synthesizers. Could you let us know the suitability of the P/N that we have chosen from TI & whether it is capable to drive 4 clipped sine wave outputs?

Regards,

Avinash

Crystal link: https://ecsxtal.com/store/pdf/ECS-TXO-20CSMV.pdf