Clock & timing forum - Recent Threads

TLC555: Component value setting

Eileen Hu — Tue, 12 May 2026 14:18:23 GMT

Part Number: TLC555

Hi team,

My customer wants to use TLC555 to generate PWM signal with 500Hz freq and 50% duty cycle. The supply voltage is 5V and no external trigger. How to set the component is suitable?

Regards,

Eileen

RE: TLC555: Component value setting

Eileen Hu — Wed, 13 May 2026 03:58:26 GMT

Hi Ron,

Thank you for your reply. If the freq is 400Hz, how to set them? The customer needs another PWM signal with 400Hz freq and 50% duty cycle, the other condition is the same.

Regards,

Eileen

RE: LMK04828: Can Not Output SDCLKoutY

馨柔 Chiu — Wed, 13 May 2026 03:36:49 GMT

In fact, we still can NOT measure exactly correct 1.5GHz clock from DCLKout0 and DCLKout2 after connecting the 1st and 2nd pole of loop filter to CPout2 pin.

We measured about 1.6GHz waveform (yellow curves) as shown in the following figures where the blue curves are measured PLL2_DLD.

LMK04828: Can Not Output SDCLKoutY

馨柔 Chiu — Fri, 08 May 2026 06:40:47 GMT

Part Number: LMK04828

Hello, I need to generate 1x, 16x clocks for AFE5828 Continuous Wave (CW) Path, whose 1x clock must be lower than 8MHz. Besides, I also need to generate SYSREF clocks to multi AFE5828 devices for JESD transmitting purposes.

The figure below shows our system layout around LMK04828L:

(LMK04828 in our system operates in single-loop mode.)

Thus, I fellow an <Setup of SYSREF Example> try to output SYSREF clocks as described in datasheet:

The following procedure is a programming example for a system operating with a 3000-MHz VCO frequency. Use DCLKout0 and DCLKout2 to drive converters at 1500 MHz. Use DCLKout4 to drive an FPGA at 150 MHz. Synchronize the converters and FPGA using two SYSREF pulses at 10 MHz.

1. Program registers 0x000 to 0x1fff as desired. Key to prepare for SYSREF operations (see Recommended Programming Sequence):

1. Prepare for manual SYNC: SYNC_POL = 0, SYNC_MODE = 1, SYSREF_MUX = 0
2. Setup output dividers as per example: DCLKout0_DIV and DCLKout2_DIV = 2 for frequency of 1500 MHz. DCLKout4_DIV = 20 for frequency of 150 MHz.
3. Setup output dividers as per example: SYSREF_DIV = 300 for 10 MHz SYSREF
4. Setup SYSREF: SYSREF_PD = 0, SYSREF_DDLY_PD = 0, DCLKout0_DDLY_PD = 0, DCLKout2_DDLY_PD = 0, DCLKout4_DDLY_PD = 0, SYNC_EN = 1, SYSREF_PLSR_PD = 0, SYSREF_PULSE_CNT = 1 (2 pulses). SDCLKout1_PD = 0, SDCLKout3_PD = 0
5. Clear Local SYSREF DDLY: SYSREF_CLR = 1.

2. Establish deterministic phase relationships between SYSREF and the device clock for JESD204B:

1. Set device clock and SYSREF divider digital delays: DCLKout0_DDLY_CNTH, DCLKout0_DDLY_CNTL, DCLKout2_DDLY_CNTH, DCLKout2_DDLY_CNTL, DCLKout4_DDLY_CNTH, DCLKout4_DDLY_CNTL, SYSREF_DDLY.
2. Set device clock digital delay half steps: DCLKout0_HS, DCLKout2_HS, DCLKout4_HS.
3. Set SYSREF clock digital delay as required to achieve known phase relationships: SDCLKout1_DDLY, SDCLKout3_DDLY, SDCLKout5_DDLY.
4. To allow SYNC to effect dividers: SYNC_DIS0 = 0, SYNC_DIS2 = 0, SYNC_DIS4 = 0, SYNC_DISSYSREF = 0
5. Perform SYNC by toggling SYNC_POL = 1, then SYNC_POL = 0.

3. When the dividers are synchronized, disable SYNC from resetting these dividers. It is not desired for SYSREF to reset it's own divider or the dividers of the output clocks. a. Prevent SYSREF from affecting dividers: SYNC_DIS0 = 1, SYNC_DIS2 = 1, SYNC_DIS4 = 1, SYNC_DISSYSREF = 1.

4. Release reset of local SYSREF digital delay. a. SYSREF_CLR = 0. Note this bit needs to be set for only 15 clock distribution path cycles after SYSREF_PD = 0.

5. Set SYSREF operation. a. Allow pin SYNC event to start pulser: SYNC_MODE = 2. b. Select pulser as SYSREF signal: SYSREF_MUX = 2.

6. After the procedure is complete, asserting the SYNC pin or toggling SYNC_POL results in a series of 2 SYSREF pulses.

However, there is not any from SDCLKoutY, Y = 1 ~ 13.

To check the digital lock detect of PLL2, I also measured output waveform from Status_LD2 pin (Pin 48) under "PLL2_LD_MUX = 0x02" and "PLL2_LD_TYPE = 3".

When I set PLL2_DLD_CNT to 1, 2, 5, the measured Status_LD2 waveforms are as follows:

PLL2_DLD_CNT = 1

PLL2_DLD_CNT = 2

PLL2_DLD_CNT = 5

I have measured OSCout (Pin 40, 41) under “OSCout_MUX = 0” and “OSCout_FMT = 1”. The measured OSCout waveform has the same frequency as that of OSCin signal.

Moreover, I have also measured waveform of SDCLKoutY under “SYSREF_CLKin0_MUX = 1” and “input 200MHz clock into CLKin0”. In this case, the SDCLKoutY did output 200MHz clocks.

If there is any mis-setting of LMK04828 leading to the SDCLKoutY can not output clocks? Thanks.

LMX2595EVM: USB2ANY firmware update failure

Hyunki Moon — Tue, 12 May 2026 01:36:49 GMT

Part Number: LMX2595EVM

Hi,

I have an LMX2595EVM with the included Reference Pro board (LMK61PD0A2). When I connect the Reference Pro via USB and launch TICS Pro v1.7.9.1, the software detects the USB2ANY interface and shows the following prompt:

"The connected USB2ANY requires a firmware update to version 2.9.1.2.
Serial Number: C4636C511B002600
Current version is: 2.7.0.0"

When I proceed with the update, it fails with "Memory verification error." The log shows:

- Password Sent Successfully
- Sending RAM BSL v00.07.88.38
- Erasing memory segments
- Sending firmware (USB2ANY v2.9.1.2)
- Firmware Sent
- Memory verification error
- USB2ANY firmware update FAILED.

After this failure, the board still enumerates as USB2ANY in Device Manager, and both LEDs (MSP430 supplied and LMK61xx supplied) are lit. The current firmware v2.7.0.0 appears to still be intact, but TICS Pro refuses to communicate (shows "Device Not Connected") because it requires v2.9.1.2.

RE: LMX2595EVM: USB2ANY firmware update failure

Hyunki Moon — Wed, 13 May 2026 02:13:53 GMT

Hi,

I tried changing the Windows language to English and retried the firmware update, but the same Memory verification error persists. Unfortunately I do not have access to a Win10 PC.

I also tried the oldest version available on the website, TICS Pro v1.7.6.2, but it also requires a firmware update and fails with the same error.

At this point, could you please provide a download link for an older version of TICS Pro that works with USB2ANY firmware v2.7.0.0? The only issue is that the current TICS Pro (v1.7.9.1) refuses to communicate without updating to v2.9.1.2, which consistently fails.

An older TICS Pro would let me use the EVM immediately while this firmware update issue remains unresolved.

Thank you.

RE: LMK00105: Availability for data transmission

Michael Srinivasan — Wed, 13 May 2026 01:36:54 GMT

Takashi-san,

The LMK00105 should be able to work with data transmission.

Thanks,

Michael

LMK00105: Availability for data transmission

Takashi Imai — Fri, 08 May 2026 07:33:15 GMT

Part Number: LMK00105

Hello,

A customer is looking for an LVDS receiver that meets the following specifications:
- Rise/Fall Time:600ps(typ)
- Power supply voltage: 3.3 V, 2.5 V, 1.8 V
- Jitter :RMS Jitter:30fs(typ)Data rate: 200 MHz (max)
- Inputs: LVDS
- Output: LVCMOS
- Input required port: 1 port
- Port requiring output: 1 port
- No guarantee of output-to-output skew

I proposed LMK00105 from here, but I was asked if it can also be used for data transmission. Although the above specification is one-way communication, is there any problem if it is used for data transmission that is continuously high/low, unlike a clock?

Thank you,

T.Imai

CDCE925: CDCE925 can generate the freq not from I2C

Sean Liao (Yu-Sheng) — Tue, 12 May 2026 04:45:24 GMT

Part Number: CDCE925

Hi sir,

Customer wants to gen 33MHz Fout, but they don't want to use SW programs through I2C method.

Therefore, is there any other better solution?

RE: CDCE925: CDCE925 can generate the freq not from I2C

Jaryd Dukes — Wed, 13 May 2026 01:07:44 GMT

Hi Sean,

We are currently looking into your query, we will get back to you within the next few days.

Best,
Jaryd

RE: LMK00105: Availability for data transmission

Takashi Imai — Wed, 13 May 2026 00:52:01 GMT

Hello,

Can anyone answer this question?

Thank you,

T.Imai

RE: LMX2820: TICS PRO2

Derek Payne — Tue, 12 May 2026 23:28:37 GMT

Then use 0.0.7 instead of 0.0.2. The User's Guide was written before 0.0.7, and 0.0.7 contains numerous bugfixes that should be used. The instructions should still be equivalent.

LMX2820: TICS PRO2

Hatice Melikoglu — Tue, 12 May 2026 16:30:52 GMT

Part Number: LMX2820

I have lmx2831 eval board. I try to test it. Users guide says that I need to choose LMX2830-TC(V0.0.2) from TICS Pro2 but it just has v0.0.1. I am wondering if I can walk through that version? Or How can I reach the LMX2830-TC(V0.0.2)?

You can see the User's guide of LMX2831 EVM

LMX283-SNAS949.pdf

LMK1D2102L: LMK1D2102L Phase noise performance with 10MHz sine input

Hashi Pro — Tue, 12 May 2026 23:04:10 GMT

Part Number: LMK1D2102L

Hi,

I am looking for replacement for LT6957-2 for squaring a 10MHz sine with low close-in phase noise. I have read through app note snaa411, and seems LMK1D1204 has poorer performance than LMK1C1102 for this application.

1) Why does LMK1D1204 have poorer phase noise performance? Is this demonstrating poor biasing, or is it inherent in the part?

2) Is LMK1D2102L likely to provide phase noise performance closer to LMK1C1102? ie being a newer, low noise part, or is there something inherent in the differential input that makes it not as suitable?

3) As I require a differential output, what is my best option here? Do you have any phase noise test data you can share for LMK1D2102L?

Thanks

LMK00306: LMK00306:Regarding unused terminals of CLKin

kakeru manita — Tue, 12 May 2026 05:53:00 GMT

Part Number: LMK00306

Dear Technical Support Team,

If only CLKin0 and CLKin0* of LMK00306 are used, how should the unused terminals CLKin1 and CLKin1* be handled?

Since CLKin_SEL[1:0] selects CLKin0 and CLKin0*, is it correct to leave CLKin1 and CLKin1* floating?

Best Regards,

RE: LMK00306: LMK00306:Regarding unused terminals of CLKin

Michael Srinivasan — Tue, 12 May 2026 22:37:31 GMT

Manita-san,

The recommended treatment is to pull both CLKin1 and CLKin1* down to GND using 1kOhm resistors.

Thanks,

Michael

RE: CDCBT1001: CDCBT1001 Application for 50ohm termination load

Michael Srinivasan — Tue, 12 May 2026 22:27:39 GMT

Hi Mike,

That should be fine.

Thanks,

Michael

CDCBT1001: CDCBT1001 Application for 50ohm termination load

Youwei Lin — Wed, 06 May 2026 06:02:37 GMT

Part Number: CDCBT1001

Hi TI team,

We are using CDCBT1001 with VDD_OUT = 2.5V to drive a single-ended 10MHz clock at 50ohm load as picture below. Vout is (2.5)(34)/(34+50)=1.5V due to voltage divider and Iout is 2.5V/(34+50)=30mA which is below maximum continuous output current 50mA, but since datasheet does not list out the recommended operating condition for VDD_OUT=2.5V, we would like to know if this 30mA would cause damage to the device and shorten the device lifetime or it is acceptable for the device under this kind of operating conditon? BTW, Is there other recommended buffer IC that is able to drive a 50ohm load under recommended operating condition...?

Thanks,

RE: TLC555: Component value setting

Ron Michallick — Tue, 12 May 2026 22:02:44 GMT

Hello Eileen,

RA = 10k

RB = 133k

RD = 301 ohms

C = 10nF

Variance from full tolerance range.

RE: LMX2492: Subsequent Ramps with Frequency Steps

Noel Fung — Tue, 12 May 2026 21:00:06 GMT

Hi There,

After RAMP_EN is programmed to 1, the device will execute the commands as set in RAMP0 to RAMP7 profiles. The device does not expect any interruption until the ramping is finished. One exception is when we have setup RAMPx_NEXT_TRIG with a trigger signal to temporary pause the ramping.

The ramp engine changes VCO frequency by adding or subtracting value (RAMP_INC) to the N divider. For up ramp, it adds value. For down ramp, it subtracts value. The process is in a continuous fashion until the RAMP_LEN counter is time out. For example, RAMP_LEN = 10 and RAMP_INC = 1MHz, then the accumulated frequency change is 10MHz. That is, the frequency has changed from F1 to F1 + 10MHz. If the next ramp is a down ramp, then the frequency is subtracted from (F1+10MHz). RST is used when the start frequency of next ramp does not equal to the end frequency of the current ramp. For example, if we want to create a sawtooth ramp, i.e. F1 to F2, then F1 to F2, ...... In this case, the start frequency of the new ramp is not equal to the end frequency of the previous ramp. This is doable as long as we have RST = 1. At the beginning of each ramp, the added N divider value is clear so the VCO jumps to the initial frequency (F1) immediately before ramping up.

The ramp engine takes care both the integer and fraction portion of the N divider, there is no overflow in numerator.

Suggest read the EVM user's guide (www.ti.com/.../snau160e.pdf) and LMX2491 datasheet (www.ti.com/.../lmx2491.pdf) for more ramp examples.

LMX2492: Subsequent Ramps with Frequency Steps

Dominik Eyerly — Fri, 08 May 2026 20:16:19 GMT

Part Number: LMX2492

Hello,

I would like to use the LMX2492 in a special ramping application. Essentially, I need to be able to increase the start frequency by a fixed step size after every ramp. The bandwidth of each ramp is identical. The time between ramps is very short, only a few microseconds so I would like to avoid reprogramming via SPI between ramps. Is this possible by simply having an up profile and a down profile that doesnt return fully to the starting position? Are there limitations? What would be the recommended approach for this?

Also, I was wondering how the external triggers from GPIOs operate. Are they sampled using the PFD clock? Are there any specifications to their setup and hold times? Thanks!

best regards
Dominik

CDC6C: 2.4GHz Emissions Causing Wi-Fi & BT Desense

Adam Lock — Mon, 11 May 2026 16:41:34 GMT

Part Number: CDC6C

Hello,

We have recently replaced our critical networking oscillators with the CDC6CE025000ADLFR. This has helped with our unit to unit clock accurancy and jitter. However, our system also has Wi-Fi and BT radios. We recently got our TIS report back and it showed a 30dB desense when measuring TIS over the air vs directly connected to the RF port.

I am seeing very strong emissions at 2.5GHz and a stong comb spectrum with my near field pobe. I am actually picking up the 2.5GHz oscillator with my probe 3' from the PCBA. I do not see the emissions in the traces leading into or out of the device. This leads me to believe they are coming from the IC itself.

My power is locally decoupled and directly connected to a large internal power plane. I will look at isolating the power for the IC locally with a ferrite and cap filter. But I do not expect this to make a significant differnce.

Do you have any insight into the emissions profile for this oscillator at 2.4-2.5GHz? Any debig recommendations?

Thank you,

Adam

RE: CDC6C: 2.4GHz Emissions Causing Wi-Fi & BT Desense

Connor Lewis — Tue, 12 May 2026 18:05:19 GMT

Hi Adam,

Unfortunately we don't have other data available on the emission profile for CDC6C aside from the CISPR-25 report that I sent in my previous reply. Just to make sure I'm understanding correctly - the CDC6C is clocking the processor, and when the processor is in reset there's no affect on emissions. When the CDC6C clock is disabled, the emissions completely disappear. Overall this points to the CDC6C being the original source of the 2.5GHz emissions and it's not likely to be anything downstream generating this noise. Does this sound accurate?

I'm not sure if this is worth trying but would it be possible to depopulate the component connecting the oscillator output to the XIN input (I believe this is C12)? I'm hoping that this could provide some more information to confirm if the 2.5GHz noise is intrinsic to the oscillator itself, or if it could somehow be coupling to the output and radiating through the output traces. Aside from that I think your strategy of testing with a passive xtal could also provide more information on where the noise originates from.

RE: LMX2820: TICS PRO2

Hatice Melikoglu — Tue, 12 May 2026 18:04:33 GMT

I have only .zip file that name 0.0.7 and when I import it. I saw v0.0.7. Can you support the 0.0.2 zip file?

RE: LMX2595EVM: USB2ANY firmware update failure

Noel Fung — Tue, 12 May 2026 17:48:21 GMT

Hi There,

We have seen this verification error problem happened more often recently, we suspect the problem might be Win11 related. However, we are not able to replicate this problem in our lab, we do not have a pin-pointing solution for this error.

Without a fix to the problem, the only thing we can do is try again with different PC. Maybe you can also try setting your pc language to English, hopefully this could fix the problem.