Clock & timing forum - Recent Threads

LMX2492EVM: Active Loop Filter Troubleshooting

Domenico Bruno — Mon, 22 Jun 2026 17:28:22 GMT

Part Number: LMX2492EVM

Hello, I am using the LMX2492, verifying wide-bandwidth applications. To acheive this, I understand that Vtune > 5V. To do this, I removed the passive loop filter and added the Active loop filter between VCP and Valf. Now, I am receiving no indication that my PLL is locked. Additionally, TP_Vtune is remaining at 0.5V, regardless of how I configure my PLL. Ive confirmed my PLL is operating by powering it on and off while observing the current draw. Beyond this, my EVM seems unresponsive. Do you mind helping me troubleshoot?

RE: LMX2492EVM: Active Loop Filter Troubleshooting

Noel Fung — Sat, 27 Jun 2026 01:35:49 GMT

Hi Domenico,

I modified a board with op-amp OPA211, it works pretty good.

To verify if the GUI is working, program the POWERDOWN bit to 0 to power down the device. If it works, current should drop. Use a scope to probe the SPI waveform to confirm there is SPI activity.

RE: LMK04828BEVM: Programming the 4828B module on CLK104 board on ZCU208 AMD board

Naveen Naraharisetti — Sat, 27 Jun 2026 00:04:57 GMT

Can you please confirm that the setting are good?

I have generated the txt file by exporting the hex file. When I am using the txt file in the BoardUI.exe from AMD the values are all zeros, but when I use the tcs file, I can see the values

Can you tell me what am I doing wrong?

LMK04828BEVM: Programming the 4828B module on CLK104 board on ZCU208 AMD board

Naveen Naraharisetti — Thu, 25 Jun 2026 11:58:47 GMT

Part Number: LMK04828BEVM

We are trying to program the CLK104 on the ZCU208 board and these are the values that we want to setup

Name	Value (MHz)
DDR ref clock	250
PL ref clock	115.2
PL sys ref	3.84
ASYSREF	3.84
ADC ref clock	115.2
DAC ref clock	122.88

I am using TICS Pro software to generate the txt file to use it in the BoardUI.exe.
Using Si570 for getting the 250MHz for the DDR ref clock
I want to use the internal ref clk TCXO, so I enabled VCO1
In order to have ADC and DAC clocks at 115.2 and 122.88, the VCO1 should be LCM(122.88,115.2)=1843.2, but this value is not in the range ((2920-3080MHz)

LMK00105: Driving four Clipped Sinewaves from LMK00105

Avinash Koushik — Fri, 26 Jun 2026 04:09:59 GMT

Part Number: LMK00105

Hi,

We want to use LMK00105 clock driver IC to drive Clipped SIne wave from a ECS-TXO-20CSMV TCXO to four synthesizers. Could you let us know the suitability of the P/N that we have chosen from TI & whether it is capable to drive 4 clipped sine wave outputs?

Regards,

Avinash

Crystal link: https://ecsxtal.com/store/pdf/ECS-TXO-20CSMV.pdf

RE: LMK00105: Driving four Clipped Sinewaves from LMK00105

Michael Srinivasan — Fri, 26 Jun 2026 23:40:28 GMT

Hi Avinash,

The LMK00105 is capable of driving 4 outputs with a crystal oscillator input. Use the XO input on the LMK00105 and you should be fine.

Thanks,

Michael

LMK3H0102: type C USB detect failure - power LED is blinking

Perlinalyn Beezley — Wed, 24 Jun 2026 21:59:37 GMT

Part Number: LMK3H0102

071.30102.M01

IC CLK LMK3H0102A01ERERR TQFN16(ROSA SV)

Initial assessment is that the issue might be related to the compatibility between the CPLD and TI components. Kindly advice if this TI IC - is being programmed by TI - or there is induced FW before to ship out to Customer ( Is this a pre programmed IC )?

RE: LMK3H0102: type C USB detect failure - power LED is blinking

Jaryd Dukes — Fri, 26 Jun 2026 22:15:15 GMT

Hi Perlinalyn,

How are you probing the output to get this oscilloscope reading? Could you share more details on your setup so we can get a better idea of how this output is being produced?

Best,
Jaryd

RE: LMK3H0102: type C USB detect failure - power LED is blinking

Perlinalyn Beezley — Fri, 26 Jun 2026 22:06:45 GMT

this is the measured freq - only 48MHz.

RE: LMK3H0102: type C USB detect failure - power LED is blinking

Jaryd Dukes — Fri, 26 Jun 2026 21:50:33 GMT

Hi Perlinalyn,

The top marking "PK3HT1" indicates that this is sample production material of the LMK3H0102. The A01E configuration should have the REF_CTRL pin (pin 15) output 50MHz LVCMOS. Can you share details on how you are probing this output, and how you are interfacing with the device?

Best,
Jaryd

CDCE6214-Q1: How to simulate CDCE6214-Q1 in Plladium?

Koen Pauwels — Wed, 24 Jun 2026 09:31:33 GMT

Part Number: CDCE6214-Q1

We are evaluating CDCE6214-Q1 on the CDCE6214-Q1EVM evaluation kit.

To assure correct operation we would like to simulate the loop filter in Plladium, however the part is not available in the tool and there are no clues in the data sheet or documentation of the evaluation kit on how to properly setup Plladium to simulate this part.

RE: CDCE6214-Q1: How to simulate CDCE6214-Q1 in Plladium?

Connor Lewis — Fri, 26 Jun 2026 20:41:16 GMT

Hi Koen,

Thanks for catching that, 60MHz/V in my last reply was a typo but I meant to say 160MHz/V since this is roughly the average Kvco across the VCO's tuning range. I'll edit my previous reply to prevent any confusion for anyone else reading this thread in the future. For your use case it's also fine to use Kvco = 175MHz/V since you know that the VCO frequency will be at the higher end of the tuning range at 2520MHz.

Your proposed loop filter looks good to me, I think this would be around the minimum BW that can be achieved with good phase margin for this device. I'll go ahead and mark this thread as resolved if you don't have any other questions.

LMK3H0102: Part with 1.2V IO/VCC

Mansoor Ahmed — Fri, 12 Jun 2026 18:17:52 GMT

Part Number: LMK3H0102

I am looking for High precision/accuracy clock generator with 1.2V single ended output for referene clock for a UFS5 device. Also a clock buffer which can support same voltage level.

Either single chip solution or multichip solution will work, please let me know.

RE: LMK3H0102: Part with 1.2V IO/VCC

Jaryd Dukes — Fri, 26 Jun 2026 18:45:33 GMT

Hi Mansoor,

Regarding your buffer for 1.8V to 1.2V LVCMOS level translation, we don't currently have a buffer that can support this translation with the rise/fall time within the 2ns specification you've provided. Do you have any phase noise requirements for the 1.2V LVCMOS output? If there are none then the LMK1C1102 could potentially be a buffer option.

I'll continue this conversation over email for more information.

Best,
Jaryd

LMK04828-EP: Clock selection logic for LMK04828

GAURAV UPADHYAY — Fri, 26 Jun 2026 12:28:06 GMT

Part Number: LMK04828-EP

Dear Sir/Ma'am,

What is the recommended approach for implementing the clock selection logic when one clock is used as the primary source and the other as a backup—hardware-based or software-based?

Best Regards,

Gaurav

RE: LMK04828-EP: Clock selection logic for LMK04828

Derek Payne — Fri, 26 Jun 2026 14:57:21 GMT

Either approach is suitable and it's a matter of preference or application requirements, which is why we implemented it both ways. I'll list some tradeoffs to help you make your choice.

	Pros	Cons
Hardware-based pin-selection	No SPI programming required after initialization, minimizing SPI traffic and any SPI crosstalk on clean outputs Could be tied to external mux/switch/relay for better noise isolation between CLKIN0 and CLKIN1 (think about the slight PPM offset spur for two 100MHz clocks) With only two clocks, can utilize one pin as reference switching, and other pin as LOS for primary pin, entirely without SPI	Debug signals must be routed out of other pins like STATUS_LDx or RESET Holdover entry is pin-controlled, so system must react quickly to loss of signal or loss of lock to avoid large phase hits from sudden signal loss No robustness advantages over SPI control (the register selecting pin-mode or software mode is just as susceptible to corruption as the register selecting which reference input to use) More GPIO routing required from controller and very slight increase to BOM cost vs. not using CLKIN_SELx pins
Software-based pin selection	CLKIN_SELx pins may be utilized as GPIO for debug/SPI/etc Can take advantage of automatic reference selection, which may not require SPI at all in many cases Less GPIO/routing required from control device if CLKIN_SELx pins are unused	Controller handles reference switching, requiring additional bus traffic, potential for crosstalk, more firmware work, etc If automatic clock switching on loss of lock is not used, holdover entry is still manual, requiring a SPI write to enter holdover; this could be slower than GPIO due to 20MHz SPI clock and 24-bit register writes Automatic clock switching on loss of SIGNAL (rather than loss of lock) requires configuring inputs in MOS mode, which can interfere with DC-coupled termination (e.g. can't put 100Ω directly across pins)

LMK04828-EP: Electrical Characterstics of Output Configuration of DCLK and SDCLK

Gireesh Kumar — Fri, 26 Jun 2026 09:36:44 GMT

Part Number: LMK04828-EP

Hi TI team,

For the below two cases 1.6Vpp LVPECL and 2Vpp LVPECL Clock Outputs,Can you provide the mathematical explanation of how VOH and VOL values for the respective test cases with derivation.

Thanks & Rewards

Gireesh

RE: LMK04828-EP: Electrical Characterstics of Output Configuration of DCLK and SDCLK

Derek Payne — Fri, 26 Jun 2026 14:34:11 GMT

A representative LVPECL driver is merely a CML network driving the base of a transistor with collector tied to VCC and emitter acting as the output pin.

To measure VOH and VOL, we arrange the following.

For the DCLKOUTX outputs:

We configure the output driver for LVPECL 1600mV or 2000mV as needed.
We attach two 50Ω resistors directly to a voltage source programmed to VCC - 2V or VCC - 2.3V as required by the output format.
We configure the device in distribution mode, with CLKIN1 configured for MOS mode, divider bypassed. This effectively functions as a direct buffer from CLKIN1 to the DCLKOUTX output under test.
We measure the voltage from the output pin to GND in the logic HIGH and logic LOW states.

For the SDCLKOUTY outputs:

We configure the output driver for LVPECL 1600mV or 2000mV as needed.
We attach two 50Ω resistors directly to a voltage source programmed to VCC - 2V or VCC - 2.3V as required by the output format.
We configure CLKIN0 for MOS mode, CLKIN0_OUT_MUX = 0 (to SYSREF distribution path), and SYSREF_CLKIN0_MUX to 1 (from CLKIN0). The SDCLKOUTY path is configured to bypass digital and analog delays. This effectively functions as a direct buffer from CLKIN0 to the SDCLKOUTY output under test.
We measure the voltage from the output pin to GND in the logic HIGH and logic LOW states.

In practice, virtually no receiver has a convenient VCC - 2V or VCC - 2.3V source to which the LVPECL output can be terminated through 50Ω. Since LVPECL requires a bias current to exit the emitter pin, our evaluation modules utilize an emitter resistor tied to GND, which results in approximately the same net bias current and voltage swing as the 50Ω to VCC - 2V case. 120Ω emitter resistors to GND and AC-coupled 100Ω differential load yields identical per-pin voltage swing (760mV for 1600mV LVPECL, 960mV for 2000mV LVPECL) to the 50Ω to VCC - 2V termination. We observe that the driver works almost as well (roughly the same phase noise performance, slightly lower amplitude) with larger emitter biasing resistors up to 240Ω, but with substantially reduced supply current. An engineering tradeoff may be made for emitter biasing resistor size between signal amplitude and current consumption of the driver.

RE: LMK04828BEVM: Programming the 4828B module on CLK104 board on ZCU208 AMD board

Derek Payne — Fri, 26 Jun 2026 14:00:12 GMT

If the ADC refclk must be 2995.2MHz, the frequency plan is unsatisfiable with any single device, because you are actually solving for LCM(122.88, 115.2, 2995.2) which is 23961.6 MHz.

Setting this aside and assuming you are just focusing on the issue with VCO1 being automatically set to 2949.12MHz: LMK04828 is a PLL, and the VCO frequency must be a multiple of the phase detector frequency. I don't know what reference frequency is provided to the LMK04828 (presumably 122.88MHz?) but the phase detector frequency should now be configured to GCD(2995.2, 122.88) = 15.36MHz. This corresponds to an N-divide of 195 and an R-divide of 8. You may need to modify the PLL2_P prescaler such that the N-divide can be realized - 195 has factors of 3, 5, and 13, so setting the prescaler to divide-by-3 or divide-by-5 should allow the appropriate N value to be realized. And make sure the PLL2_N_CAL value is programmed to the same value as PLL2_N, to ensure the VCO calibration yields the best noise and temperature performance.

RE: LMX2492EVM: Active Loop Filter Troubleshooting

Domenico Bruno — Fri, 26 Jun 2026 13:58:40 GMT

The opamp Bias is derived from a voltage divider. Im expecting a value of 2.5 since Vcc is 5, I am receiving that. Vcp is reading 1.9V, Im unable to measure the current. However, the active filters output remains railed regardless of the input provided on the GUI. It seems that the PLL is no longer receiving SPI communication.

RE: CDCE6214-Q1: How to simulate CDCE6214-Q1 in Plladium?

Koen Pauwels — Fri, 26 Jun 2026 08:19:36 GMT

Hi Connor,

Thanks for the answer, I really appreciate the time you took to look into this!

We started with checking the pre-set configurations from table 7-3 in the datasheet, but had the impression none of them fitted our application.

In the meantime we experimented with TICS Pro, PLLatinum and the CDCE6214-Q1EVM and came up with following settings:
- Filter Architecture: 3rd order passive
- Kpd: 600 µA
- C1: 11.76 pF
- C2: 941.1 pF
- C3: 2.9 pF
- R2: 1 kOhm
- R3: 2 kOhm
- Kvco: 175 MHz/V
- VCOCap: 0 pF

Simulation results:
- Loop bandwidth: 333.1573 kHz
- Phase Margin: 61.9°

These settings have been tested on the CDCE6214-Q1EVM in a temperature sweep between -40°C and +105°C. The PLL kept phase lock across the complete temperature range, with a max phase variation below ±1.5ns measured on scope.

The loop bandwidth is higher than ideal, but still acceptable. Unless you see a problem with this setup, we would like to stick to this. Our main driver to pick the CDCE6214-Q1 was our required temperature range of -40°C to +105°C.

One more question: The data sheets states KVCO values of 140 MHz/V @ fVCO = 2.4 GHz and 175 MHz/V @ fVCO = 2.5 GHz can you clarify why you propose to use 60MHz/V ? Did I misinterpret the data sheet or did you intend to write 160 MHz/V as a safe value to take tolerances into account?

RE: LMX2492EVM: Active Loop Filter Troubleshooting

Noel Fung — Thu, 25 Jun 2026 23:36:16 GMT

Hi Domenico,

The GUI issue can be fixed by closing TICS Pro and re-open it or even do a PC reboot. The GUI does not care whether we use active or passive loop filter, If the configuration works on passive filter, then the same configuration should work on active filter with appropriate CP polarity.

Did you try changing the op-amp bias to 2.5V?

LMX2572: Follow up question

John Roulston — Wed, 24 Jun 2026 20:28:18 GMT

Part Number: LMX2572

Hi Noel,

Thank you for pointing us to SNAA336. We note that it covers the LMX2594/2595/2615-SP family. Does the full assist technique described in §3.3 apply equally to the LMX2572, and if so, are the equivalent register addresses documented? This is really significant in adhusting phase to make 2 stepped frequency sources mutually coherent and still meet a tight transition timeline.

Regards,
John Roulston
Rodradar Ltd

RE: LMX2572: Follow up question

Noel Fung — Thu, 25 Jun 2026 23:27:21 GMT

Hi John,

Yes, the appnote applies to LMX2572.

Related register fields in LMX2572 are shown in below.

RE: LMX2572: Cat3 phase sync not reliable

Noel Fung — Thu, 25 Jun 2026 23:21:53 GMT

Hi There,

The readback data looks normal.

Yes, we need to use a scope to verify if the phases are indeed deterministic.

According to you register setting, MASH_RST_COUNT is 36863 or 368.63µs. Try make it longer to see if that helps.