https://e2e.ti.com/support/clock-timing-group/clock-and-timing/ Products covered in this section are Clock Generation & Distribution, Memory Interface, Registers, Real Time Clocks and Timers. en-USTelligent Community 13https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654726/lmk6c-oscillator-for-dp83867ir/6381609Fri, 12 Jun 2026 22:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d3b5456c-3f45-4d7a-960d-6beafeee1f3cJaryd DukesHi Ishiwata , The LMK6C should be sufficient to interface with the DP83867IR, as it can be configured output the 25MHz oscillator input frequency needed by the part. Our ethernet team is more familiar with our PHY portfolio that would allow you to enable 1G/100M/10M Ethernet communication via RGMII, please feel free to reach out to them for PHY support. As for our BAW oscillators, the LMK6C or CDC6C are good options for LVCMOS output depending on the performance, power consumption, and jitter you require from the oscillator. Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654727/lmk61a2-100m-oscillator-for-agilex-5/6381590Fri, 12 Jun 2026 21:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:91d731ea-6725-4222-a168-319f62efa486Jaryd DukesHi Ishiwata , We're looking into your inquiry, we'll get back to you early next week. Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1652132/lmk04832-lmk04832-sysref-phase-alignment-not-working/6381544Fri, 12 Jun 2026 20:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8b397cfb-e3fc-48d1-87d2-e3d72387ecddDerek PayneUnderstood. 150ns is still more than enough time, one-shot or not. The one-shot is triggered on any rising edges at the SYNC source, and does not latch - once the one-shot duration completes, another rising edge can trigger it again. I don't think it is retriggerable while the output is high, but I have never tested pulses short enough for it to matter. Anyway, for a situation with the one-shot enabled where the time between 0x144 -> 0x00 and 0x144 -> 0xFF is multiple seconds, you would expect to see multiple pulses out of the device. Observed behavior is consistent with expectations, at least on this small part of the puzzle. I will await results of the CLKIN0 test.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654102/cdcs503-the-output-oscillates-even-though-there-is-no-input/6381403Fri, 12 Jun 2026 18:49:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d0708af0-9b69-4cb2-a719-a0dbf3611d9dJaryd DukesClosing this e2e post since this conversation has continued over email. For reference, this should be the expected behavior of the part. Internal to the CDCS503 is a PLL that stabilizes the output frequency and SSC capabilities of the part. In this part, the PLL does not have a holdover mode or input loss detection to mute the clock output, so when the input reference is disconnected the output will continue in an unstable, free-running mode. If you are looking to mute the output when there is no clock input, it would be best to pull-down the OE pin when the FPGA clock input is no longer being provided.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1655039/lmx2595evm-output-filter-pl-lmx2595/6381379Fri, 12 Jun 2026 18:18:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f7e82ae6-afda-490d-a399-3643fbff8126Derek Payne[quote userid="530666" url="~/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1655039/lmx2595evm-output-filter-pl-lmx2595"]Could you also clarify whether the RF output can essentially be considered the collector node of a transistor within the output buffer stage?[/quote] Yes, these are open-collector outputs, and the output pin is on the collector node. [quote userid="530666" url="~/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1655039/lmx2595evm-output-filter-pl-lmx2595"] My assumption is that L1 and C6 form a filtering network that either prevents RF energy from leaking into the supply rail, suppresses noise coming from the supply, or improves the RF performance of the output stage in some other way. [/quote] If no inductor was present, the capacitor in the L-C network would just be rolled into the bypass network; any small variations in output driver current or tolerance-related effects from resistor/transistor mismatch are smoothed out by the low-inductance bypass network, simultaneously containing RF energy and modestly improving common mode rejection (thus supply noise reduction). But because the inductor is also part of the pull-up network, the extra capacitor must be used as the equivalent of the bypass capacitor for the pull-up resistors, since the loop inductance through the pull-up inductor would otherwise be large enough to diminish the efficacy of the existing supply bypassing. So why have the inductor at all? It turns out that purely-resistive 50 Ω pull-ups are not that well-matched to the LMX2594 output stage at higher frequencies, after accounting for package and driver parasitics. Several years ago a colleague wrote up a detailed document about output power behavior, which elaborates on the need for inductive pull-ups to maintain output power at high frequencies (see below) - in particular, refer to Chapter 4. e2e.ti.com/.../0535.High-Frequency-Open-Collector-Outputs.pdf Subsequent devices such as LMX2820 have moved the pull-up components into the output stage, greatly simplifying layout and improving the overall power flatness across frequency. If the external pull-up network is burdensome, the LMX2820 and other newer synthesizers may be worth considering for present or future endeavors.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1655066/lmk3h0102-part-with-1-2v-io-vccFri, 12 Jun 2026 18:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:81ff1f2e-a6b3-4f74-8272-32e54ce06353Mansoor AhmedPart Number: LMK3H0102 I am looking for High precision/accuracy clock generator with 1.2V single ended output for referene clock for a UFS5 device. Also a clock buffer which can support same voltage level. Either single chip solution or multichip solution will work, please let me know.Home theater & entertainmentLMK3H0102https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654168/lmk5c23208a-layout-review/6381370Fri, 12 Jun 2026 18:05:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9dc55f02-d7cf-4690-a4de-ca9304dd9affJaryd DukesHi Abhishek, Yes the configuration file can be made with TICS Pro. If you're using an EVM to test/evaluate the chip, you can use the LMK5C33216A EVM with the LMK5C23208A TICS Pro device profile since they use the same silicon core and pin layout. The schematic looks good for the most part, here are my comments: I noticed the I2C pullup resistors are depopulated; since the design uses I2C, the pullups on the I2C lines are needed for I2C to function properly. Although you are not using IN0/IN1, VDD_IN needs to be connected to VCC for PD# to be pulled up. The ferrite bead is optional if IN0/IN1 are unused. Here are my layout comments: Make sure to place the 0.1uF bypass capacitors near the supply pins of the device, and use wider polygons for the VDD lines. The layout is quite dense for such a large board, are you adding other parts to the entire board later? The differential traces need to be spaced to ensure there is 100Ω differential trace impedance across the signal pairs. If components are depopulated in the schematic, ensure they are also depopulated in the layout. This portion of the layout appears to be incomplete, please double-check the routing of OUT5 Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1655039/lmx2595evm-output-filter-pl-lmx2595Fri, 12 Jun 2026 16:09:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:44653caf-9891-4c18-841d-070b9a133798Josel GoPart Number: LMX2595EVM Other Parts Discussed in Thread: LMX2595 , LMX2594 , LMX2820 Hi Experts, I am currently developing a transmitter based on the LMX2595 PLL and have a question regarding the output circuitry shown in the datasheet and on the LMX2595EVM. According to the datasheet, the RF output stage is implemented as an open-collector output and therefore requires a pull-up element (resistor or inductor). This part is clear to me. However, when looking at the LMX2595EVM schematic, I noticed that in addition to the pull-up resistors (R37 and R38), there is an inductor (L1) connected from the center node between these resistors to VCC, as well as a capacitor (C6) connected from the same node to ground. Could you please explain the purpose of these additional components? My assumption is that L1 and C6 form a filtering network that either prevents RF energy from leaking into the supply rail, suppresses noise coming from the supply, or improves the RF performance of the output stage in some other way. Could you also clarify whether the RF output can essentially be considered the collector node of a transistor within the output buffer stage? These additional components make the RF layout somewhat more challenging, so I would like to understand whether they are generally required, what performance benefits they provide, and under which circumstances they could potentially be omitted. Thank you very much for your support. Kind regards, Robin SauerzapfLMX2594LMX2820LMX2595LMX2595EVMhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654818/lmx2572lp-current-reduction/6381189Fri, 12 Jun 2026 15:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4bf8c9b7-c0f8-4037-8dee-e8b7758d677eNoel FungHi There, All supply pins are required. If you do not require a wide loop bandwidth, you can use a smaller charge pump current to reduce overall current consumption. A lower reference clock and phase detector frequency can also reduce the current.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654850/lmx2594-regarding-the-output-power-of-the-lmx2594/6381149Fri, 12 Jun 2026 15:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:62e2842f-aa65-453d-9108-ee8ef0112ec0Noel FungHi There, For sine wave signal, when converting voltage to power, the voltage is measured in rms. So, P(W) = (V / sqrt2) 2 / R. 5dBm sine wave --> 1.124683Vpp. Output power changes with register setting, below Figure shown the approx. power change vs setting.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654672/lsf0101-level-translator-for-40mhz-clk/6381106Fri, 12 Jun 2026 15:07:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ea421e46-7c54-4b95-9b31-15a9a25c4e5eJack GuanHi D, We will get back to you shortly. Regards, Jackhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1651880/ds110df410-ds110df410sq-nopb/6380938Fri, 12 Jun 2026 12:43:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1eb92f19-57d1-4642-b462-e258c7910291prajesh pCould you please suggest a retimer IC that is capable of supporting all the link rates listed below? Bit Rate (Gbps) ---------------------------- 1.0625 1.5 1.62 2.125 2.5 3.1875 4.25 5 6.375 8.5 10https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654168/lmk5c23208a-layout-review/6380892Fri, 12 Jun 2026 11:51:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:77a903eb-47fc-4ece-a28b-06d0c83263bfAbhishek ManojHi Jaryd, Thanks for the reply. Meanwhile can you please guide me how to make the clock configuration file for LMK5C23208ARGCR . It need to be done in TICS pro tool right. Please provide the support and necessary steps to proceed. Regards, Abhishekhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654850/lmx2594-regarding-the-output-power-of-the-lmx2594Fri, 12 Jun 2026 08:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:04342098-1ed5-418a-9353-d7df7f73c2c5Yabe MasamiPart Number: LMX2594 Regarding Pout, I would like to know the voltage level instead of dBm. Is the following conversion formula correct? Especially, whether dBm should be converted using 10log or 20log often varies depending on the manufacturer, so I would like to hear your company's approach. For 5dBm, R=50ohm P(mW)=10^(5/10)=3.163378mW V = sqrt(P * R)=0.3976365V Therefore, Vdiff_p-p=0.3976365 * 2=0.79527V Is this formula correct? Regarding Pout, the specification is given for OUTx_PWR = 50, but in our application, we use OUTx_PWR=19 and OUTx_PWR=29. What would the output be for these settings? It does not have to be an exact value an approximate ratio compared to OUTx_PWR=50 would also be helpful. Could you please provide this information?LMX2594Wired networkinghttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654818/lmx2572lp-current-reductionFri, 12 Jun 2026 06:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:820c49bd-abc5-4ca3-aacd-23d003dbbeaeuser4852208Part Number: LMX2572LP I'm considering reducing the current. The current settings are as follows: 1. RFout = 1500~1600MHz 2. REF = 32MHz 3. Output level = -3 dBm typ. 4. total current = 80mA typ. I'd like to explore whether the current can be reduced further. Pins 26, 27, and 29 are labeled VCO2, and pins 36, 37, and 3 are labeled VCO. Since only the top VCO is used between 1500 and 1600MHz, is it possible to cut off the power supply to one of them?LMX2572LPTest & Measurementhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654755/lmk3h0102-p2p-with-fgv1006cqFri, 12 Jun 2026 01:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b072c84a-29c7-444e-9f12-579563e9acdaShuhei GotoPart Number: LMK3H0102 Hi team, Please provide information on the compatibility between FGV1006CQ and LMK3H0102. We are considering using these with a common footprint in a B2B configuration. https://www.renesas.com/en/document/dst/9fgv1002c-9fgv1006c-datasheet?srsltid=AfmBOoq_1BxI0QKJzQCmhz8Qa0jMNbCdeoIDQ-tOg7nMVGy46ZBsrf5U [Q1] Pin1 and Pin2 are NC on the FGV1006CQ. Pin1 of LMK3H0102 seems to have no issue being NC (floating), but will the device operate correctly if Pin2 is also NC? [Q2] How do the OPN variants correspond to each other respectively? The following is my understanding, but are there any misunderstandigs? LMK3H0102V33RERR - FGV1006CQ505LTGI LMK3H0102V33RERR - FGV1006CQ515LTGI (Can we change output impedance by OTP?) LMK3H0102V18RERR - FGV1006CQ506LTGI Best regards, GotoLMK3H0102https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654505/lmk5b33414-lmk5b33414rgcr-minimum-system-design-consultation/6380270Fri, 12 Jun 2026 01:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c473c19c-0c40-4531-b563-cc8adca1312dJaryd DukesHi Lu, We're looking into your schematic, we will get back to with feedback early next week. Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654653/lmk5b33216-schematic-review/6380232Fri, 12 Jun 2026 00:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:397a93e5-a8fb-4ecd-93c8-63f05c921a16Jaryd DukesHi Sky, Yes you can use a 10MHz OCXO as an XO input as long as the frequency has a non-integer relationship with the VCO frequencies of each of the APLLs (if the DPLLs are being used). I will review the schematic you've sent and get back to you with feedback in the next few days. In the meantime, would you be able to send a clearer image or a PDF of the schematic? Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1645331/cdce6214-cdce6124-syntonized-clock-servo/6380198Thu, 11 Jun 2026 23:44:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0a117cd7-762b-4b07-98e4-32b3f15417eeJaryd DukesHi Tobias, It seems like your methodology is once again correct; I'll investigating internally why the DCO mode configuration in pin mode is not properly incrementing the output and I'll get back to you as soon as possible. Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1654727/lmk61a2-100m-oscillator-for-agilex-5Thu, 11 Jun 2026 23:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:527c49ff-381f-453f-9efb-6ad93e676cf8Shuji IshiwataPart Number: LMK61A2-100M Hi All, I'm looking for a 100MHz oscillator that satisfies the I/O PLL requirements of the Agilex 5. Is the LMK61A2-100M00 usable with the Agilex 5? The specifications listed in "Table 53. E-Series FPGAs I/O PLL Specifications" https://docs.altera.com/r/docs/813918/current/agilextm-5-fpgas-and-socs-device-data-sheet/i/o-pll-specifications • tINCCJ • tREFPJ • tREFPN Does the LMK61A2-100M00 meet the above specifications? It seems that all except tINCCJ meet the specifications. Best Regards, IshiwataLMK61A2-100MTest & Measurement