https://e2e.ti.com/support/clock-timing-group/clock-and-timing/ Products covered in this section are Clock Generation & Distribution, Memory Interface, Registers, Real Time Clocks and Timers. en-USTelligent Community 13https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1648084/lmk04828-maximum-oscin-frequency/6356863Sat, 23 May 2026 22:03:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:45ca77a6-1a29-4c3d-82c5-c4a35aba5d48Kevin SavageHi Derek, Thank you for the very informative and rapid response. I will try 600 MHz and see how it goes! As for the state machine max clock rate, if it is an issue that could be present over PVT, your proposed workaround of performing a one-off calibration at lower OSCin, storing in NV, and setting this manually going forward, sounds like something we would be keen to explore. We currently follow a similar scheme for other synths/PLLs within our system but have never done this for an LMK0482x. If it is possible to provide brief documentation on the expected process that would be very useful! Thank you for any information you can provide. Kevinhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1644377/lmx2594-inquiry-regarding-the-synchronization-of-rest-of-channel-divider-with-sysref-in-lmx2594/6356766Fri, 22 May 2026 23:41:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cdcde5dc-2d4d-43f8-9cb5-516f359e08c2Noel FungHi There, The skew between output A and B (sysref) changes with the rest of the divider value but this skew remains unchanged over power cycle.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1646676/lmx2572-lmx2572-output-skew-between-rfouta-and-rfoutb-used-as-sysref/6356759Fri, 22 May 2026 23:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ae989ed3-c95c-4e69-82e4-ce3023a2d4ebNoel FungHi Wenhao, We don't have the PVT data for the skew between RFOUTA and RFOUT (sysref). The measured skew is 880ps on an EVM. Changing the MASH_SEED would not change the phase between output A and B.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1647439/lmk04832-pll-failing-to-lock-at-certain-phase-detector-frequencies/6356722Fri, 22 May 2026 22:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f7044bb3-ae84-4d2b-93c9-94aa7c0b93a5Noel FungHi Justin, I can get the EVM locked with your 50MHz configuration. Your normal 122.88MHz configuration also works. You are using the Status_LD2 pin as lock detection, you can monitor this pin with a scope so we know if this pin stays HIGH during the system failure. The Si device also support lock detection and LOS detection, you can also monitor these outputs to verify if the unlock also happen on this device.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1647097/lmk04610-calculating-the-loopbandwidth/6356655Fri, 22 May 2026 20:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9a5b70c1-044c-4df2-b3c6-b88ab898047bNoel FungHi There, PLL1 is used as a jitter cleaner, the output phase noise is basically equal to the phase noise of the VCXO, as long as the loop bandwidth is very small. Typical loop bandwidth for this application is below 20Hz. If the loop bandwidth is 20Hz, then the phase noise of PLL1, after 20Hz, is equal to VCXO phase noise. You can also use any loop bandwidth you want, just tell TICS Pro and click the Find PLL1 Settings button. For example, 100Hz bandwidth. 10Hz bandwidth.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1648097/lmx2572-phase-adjustment-and-mash_seed-value/6356633Fri, 22 May 2026 20:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:66578ce0-f44d-4676-a374-37a3243ddfccNoel FungHi There, MASH_SEED gets reset whenever a VCO calibration is executed. Phase adjustment has to re-do again after calibration.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1648151/lmx2820-spi-programming-sequence/6356628Fri, 22 May 2026 20:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4c1614f2-75c8-4644-8c3c-052d42abe5d0Noel FungHi There, As long as the timing meets device requirement, it does not matter whether the SPI signals came from dedicated SPI port or IO port of the logic device.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1648592/lmx1205-issues-with-the-ibis-model/6356611Fri, 22 May 2026 20:16:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:683f0fed-8f57-42fb-b5e0-f0cf1cbb6b4bNoel FungHi There, There is no issue on my side.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1646751/lmx2594-phase-synchronization-of-2-lx2594-output/6356597Fri, 22 May 2026 19:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b1312471-91ad-4c43-88ee-311afdee14a3Noel FungHi Yoda-san, CPout must connect to Vtune via the loop filter, otherwise the pll is never locked. Others are good, also need to make sure the exposed pad is connected to the ground plane.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1642907/lmk05318bevm-spikes-observed-in-the-phase-noise-of-100-mhz-output-from-lmk05318b-eval-board/6356343Fri, 22 May 2026 16:23:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:04fa2795-e043-4452-ad94-305f3ea143adConnor LewisHi Suchitra, Thanks for the update here. Unfortunately I don't have access to a phase noise analyzer today, and Monday is a holiday so I won't be able to do any experiments on my setup until Tuesday at the earliest. It sounds like with the latest config file, the spurs show up whenever the device enters holdover for both the auto non-revertive and manual holdover modes. When the device is in holdover can you try reading back PLL1_NUM_STAT? The easiest way to do this is on the "Raw registers" page in TICS Pro, you can enter PLL1_NUM_STAT and the field name on the right side of the screen and click "read" to get the live status of this field. I'm wondering if the DPLL is somehow setting a non-optimal APLL numerator value which introduces spurs on the output. This seems unlikely to me since you don't see a frequency offset on the clock output, but it's worth double checking. Also, do the spurs change when you toggle a soft reset? I would be interested to see if toggling soft reset after updating the reference switchover mode or after the DPLL enters holdover shows any improvement.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1646751/lmx2594-phase-synchronization-of-2-lx2594-output/6356179Fri, 22 May 2026 14:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:12f3eb26-044d-47fd-a75b-3bd0493aab2fYoda YukihideDear Noel Thank you very much. Your advice is very helpful. I have a follow-up question. Even after following your advice and enabling VCO_PHASE_SYNC = 1, we have found that our current circuit may be experiencing the following problems: 1) 4096MHz and 1638MHz are not being generated accurately. The frequencies are higher than the target (potentially +8~16MHz higher than expected). 2) 4096MHz and 1638MHz are not synchronized. *We do not yet have a high-speed oscilloscope, so we have not been able to measure the quantitative error. The setting is VCO_PHASE_SYNC = 1, and the other parameters are as shown in the table above. While investigating the cause, we found the following problem in our circuit: Possible problem: The CPOUT pin is not connected to the VTUNE pin. (The following diagram shows our circuit.) Question: 1) What impact could the fact that the CPOUT terminal output is not connected to VTUNE have on our current design goals? 2) Is there a setting that would allow us to achieve our design goals without any problems even if the output of the CPOUT terminal is not connected to VTUNE? 3) Could you please check if there are any other problems with our circuit?https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1648625/lmk04610-selecting-clock-synthesis-partFri, 22 May 2026 13:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d080740c-66fc-41b4-acfd-4c414bcee269gurudatta pPart Number: LMK04610 We have a requirement of clocking high speed ADC on an FPGA SoC Clock requirement are as follows: 1. Sampling clock for ADC: 2GHz or 4 GHz, 1 output phase noise profile for 2ghz is: 100hz -103.08 1khz -112.08 10khz -120.08 100khz -123.08 1mhz -143.08 10mhz -144.08 100mhz -164.08 At 4Ghz: 100hz -103.06 1khz -112.06 10khz -120.06 100khz -123.06 1mhz -141.06 10mhz -142.06 100mhz -158.06 1.SYSREF frequency pulsed: 250Mhz, 2 outputs 2.SYNC clock: 500MHz, 2 outputs 3.All clocks to be in sync 4.We are planning to use a 10MHz OCXO with the following phase noise profile as the source clock 10hz -130 100hz -155 1khz -166 10khz -173 100khz -175 5.Also provide simulation files if possible Please suggest a device for clock synthesis from your portfolio.LMK04610https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1648592/lmx1205-issues-with-the-ibis-modelFri, 22 May 2026 11:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:71b45393-18e6-4875-bd5b-c1889f28924fMatteo RicciPart Number: LMX1205 Hi team, i'm using the IBIS model of the LMX1205. I try to simulate the CLKOUT model: i selected the pin 18 and 19. I attach the electrical schematic. The port number 3 is the signal source (square wave with frequency of 5 GHz). At the ouput of the model, i'm not getting a correct waveform. Why? Do you see some problems with my settings? I try to use another ibis model (LMK04610RTQ) and it works correcty. Can you help me? Thank you in advance. Best Regards, Matteo RicciLMX1205Aerospace & Defensehttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1642907/lmk05318bevm-spikes-observed-in-the-phase-noise-of-100-mhz-output-from-lmk05318b-eval-board/6355759Fri, 22 May 2026 08:08:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a25e99b3-3a9a-405b-8878-9fa294fd5444Suchitra RamamoorthyHi Connor, We tried the changes that were suggested earlier regarding the Auto Non-Revertive / Holdover configuration. The following steps were performed on our side: Enabled SECREF Applied the frequency detector to SECREF Configured the device in Auto Non-Revertive mode Removed the 10 MHz reference input This time, the GUI correctly indicated “Holdover Mode” after the reference removal, which confirms that the holdover detection mechanism is functioning properly. However, the phase noise issue still persists. The unwanted spurs/spikes continue to appear even while the device is in Holdover mode. Earlier, we suspected that the mode transition itself was not occurring, but now the GUI acknowledgement confirms that the transition is happening correctly. Since the issue is not observed on your setup, we would like to understand whether there could be: Any hardware-related issue on our evaluation board Any specific jumper configuration or board modification required Any firmware/software update needed Any dependency related to the GUI version, drivers, or laptop setup Any additional initialization/configuration steps being performed on your side that we might have missed Additional information from our setup: External 10 MHz reference applied through SMA External 48 MHz OCXO reference applied through SMA Holdover mode acknowledgement is visible in GUI Spurs remain visible in phase noise after reference removal This project is currently in the integration stage, and resolving this holdover mode issue is extremely critical for us at the moment. We would highly appreciate your guidance on the exact configuration or debugging steps required to eliminate these spurs. Please let us know if you need: Register dump Configuration file Phase noise plots Spectrum screenshots Oscilloscope captures Board photographs Also, since this is an evaluation module, if the observed behavior is eventually traced to a hardware fault or anomaly specific to our board — especially considering the issue is not reproducible at your end — then we would also like to discuss the possibility of warranty support or replacement of the evaluation module. Looking forward to your support. Regards, Suchitra Ramamoorthy.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1648084/lmk04828-maximum-oscin-frequency/6355660Fri, 22 May 2026 06:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4e399ffd-6604-49f7-b0d1-bede2684a0cfDerek PayneWhile you're welcome to try it and see if it works, we can't make any guarantees that the device will meet the specs in the electrical characteristics. The OSCin input stage is largely a copy of the CLKin input stages at the design level, which are suitable up to 750MHz. The PLL2 R-divider is also unlikely to be a problem, and the PLL1 N-divider is definitely not a problem. The OSC_2X multiplier will not work reliably at these frequencies and should not be used. I'm not sure OSCout can support >500MHz, I've never tried. The FB_MUX can drive OSCout, and those clocks can be >500MHz, so I think it should work. There is a state machine clock divider tapped from the OSCIN port, which divides the clock input by 1, 2, 4, or 8. This state machine clock is supposed to stay below 65MHz to reliably calibrate the VCO when writing the LSBs of the PLL2_N field. At 600MHz, the state machine clock at maximum division is 75MHz, which may cause the calibration to fail or become stuck, which may leave the PLL in an unknown state until reset/power cycle. In principle, it is possible to calibrate the VCO at a lower OSCIN frequency that results in the same VCO frequency, read back the calibration results, and subsequently configure the device to skip calibration while manually entering VCO calibration coefficients. These coefficients should not change over the lifetime of the device, and depend heavily on the temperature at which the calibration is performed; if a fixed set of calibration coefficients is to be used, they should be derived at around the midpoint of the operating temperature range expected in the application. Of course, the calibration coefficients are derived for a specific VCO frequency - if a large range of potential VCO frequencies is needed, it may be feasible to generate a per-device lookup table for each required value. I don't know if we have ever documented the process of overriding calibration coefficients for LMK04828, but if this is of interest I can put something together for you.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1647993/cdclvp1102-need-life-cycle-expectancy-data-for-the-below-part-numbers/6355388Fri, 22 May 2026 03:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d31538f2-c35c-469f-b0b9-9792f0420b1fKumar swamyHi Michael, Thanks for the response. But I have question I asked is if the parts are in active status, how long it will be in production. I am doing redesign and this is required to manage obsolescence. Provide the extected years of production for below parts. Regards, Kumarhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1647228/lmk1c1104-part2-recommended-clock-buffer-for-distributing-one-8mhz-clock-to-four-mcus/6355233Fri, 22 May 2026 00:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2191b628-47ac-487b-8680-9f3f913bbca7Michael SrinivasanHi Conor, Sorry for the delay on that first post. 1. The LMK1C1104 is recommended for your use case. 2. Yes, that would be acceptable. 3. We do not have a 5V LVCMOS buffer that can support frequencies as high as your use case. Thanks, Michaelhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1647994/cdclvp1102-need-life-cycle-expectancy-data-for-the-below-part-numbers/6355231Fri, 22 May 2026 00:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0c577ab8-31dd-46af-85be-b1d41e6a771fMichael SrinivasanClosing this thread as it is a duplicate. Thanks, Michaelhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1647993/cdclvp1102-need-life-cycle-expectancy-data-for-the-below-part-numbers/6355230Fri, 22 May 2026 00:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:abb2197c-9892-4d38-9809-6dbc6ed14207Michael SrinivasanHi Kumar, Here is the information we have for the CDCLVP1102: Thanks, Michaelhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1647439/lmk04832-pll-failing-to-lock-at-certain-phase-detector-frequencies/6355209Thu, 21 May 2026 23:51:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f472197b-0ef5-4e0a-a771-8b7083f46dd6Justin SolimanHi Noel, Thanks for the reply! The image I sent is of our nominal configuration where we use a phase detect frequency of 122.88MHz. When attempting to try lower phase detect frequencies, i used the PLL2_R divider as you mentioned but still saw failures to lock at the various frequencies mentioned above. Attempting to isolate those failures to the LMK, I bypassed the SI5345 by feeding a 50MHz TCXO straight into the LMK into CLKin1, and still saw total failure to lock (I did not use any R dividers in that case at all). It appears to be something more nefarious, would you mind taking a look at the 50MHz TICS file i sent? As far as the micro unlocks, they appear to last about 10us per a capture in zero span mode (I cant seem to upload pics in this comment). Which pin would i monitor to detect micro unlocks in the LMK04832? I only see programmable pins 1 and 2, not sure how to use those. Ideally I want to drive the LMK directly with a TCXO to determine if the micro unlocks are coming from the LMK or SI5345, but I cant get the LMK to lock in the first place! Thanks for your help!