https://e2e.ti.com/support/clock-timing-group/clock-and-timing/ Products covered in this section are Clock Generation & Distribution, Memory Interface, Registers, Real Time Clocks and Timers. en-USTelligent Community 13https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692081/lmk05318b-request-for-certificate-of-volatility-for-lmk05318brgz/6520084Fri, 23 Oct 2026 18:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5b2fe256-6c21-457f-a9af-27ae0a629854Jaryd DukesHi Wang, I will check with our product engineering team if we have this certificate and get back to you shortly. Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1691777/mspm0-sdk-mspm0l1306-is-gpio-wake-up-detection-in-standby0-mode-based-on-a-32-khz-clock-or-asynchronous-logic/6520057Fri, 23 Oct 2026 18:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5fa2f8ef-ac48-411d-8879-9cae9c296057Brian DempseyHi, thanks for the question. With GPIO fast wake enabled and asynchronous requests allowed in SYSCTL, the MSPM0L1306 can request SYSOSC without waiting for a 32-kHz sampling edge. However, normal GPIO input processing still uses a two-stage ULPCLK synchronizer and optional filtering. The fast-wake request is asynchronous—not the entire input-to-interrupt path, so this does not guarantee zero jitter. TRM §9.2.3–9.2.4 . The datasheet specifies 15 µs typical from GPIO edge to first CPU instruction with filtering disabled and fast wake enabled. It does not specify a guaranteed jitter bound. Also observe GPIO_ERR_01 for repeated wake events: deassert the wake input while the MCU is active before returning to low power. Its three-LFCLK-cycle restriction concerns rearming, not initial wake latency. Errata, page 14 . Hope this helps! -Brianhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1686352/lmk03318-lmk03318-ac-lvds-output-skew-if-not-in-divider-value/6520036Fri, 23 Oct 2026 17:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:03db45c1-ae39-44d3-8e24-800560c5cd84Brian MaceHi Li, Sorry for the delay here this got lost in my email. I have confirmed that the delay between divider values that are close is very small, but it is hard to give an exact value without knowing the exact divider values. We would expect that using different divider values shouldn't add more than ~100ps. So the skew between outputs, even running different divider values, shouldn't be more that ~200ps (100ps + 100ps datasheet limit). Realistically is should be much less (likely within the 100ps original spec), but we cannot guarantee that. Best, Brianhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692267/lmk1c1106-lmk1c1106-lmkdb1104-lmkdb1102-olb-file/6520025Fri, 23 Oct 2026 17:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:dee080a7-a357-4774-8744-7bf038b0f18bNirmal Karthike2e.ti.com/.../ORCAD-Captures.zip Hi Sean, Attached is a zip with the olb files for each part. For future reference, you can find these on each part's website. Looking at the LMK1C1106 as an example: 1. Navigate to the product website and click on "Design & development" 2. Select the header for CAD models: 3. Click on the UltraLibrarian Link to get access to the portal to download design files: Hope this helps!https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692260/lmx2595-current-consumption/6520012Fri, 23 Oct 2026 17:20:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:15d60661-4076-41ae-acdb-4acc93785803Noel FungHi There, suggest use TICS Pro ( www.ti.com/.../TICSPRO-SW) to estimate the current consumption based on the actual application configuration.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1691983/lmx2594-lmx2594-ramp-limit-low-and-high/6519998Fri, 23 Oct 2026 17:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:43d8d0d8-e491-498c-ab26-0154ec75ec5fJim Maynene2e.ti.com/.../Ramp-sketch.pdf We are configuring symmetrical ramps with frequency excursion of 10MHz up to 100MHz, and repetition rate of 500Hz up to 5kHz, or any combination in between. No trouble with creating these ramps, just want to understand any known limitations with the Fhigh / RAMP_LIMIT_HIGH setting. Thanks.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692118/lmk1c1102a-lmk1c1102adqfr-output-enable-of-this-ic/6519971Fri, 23 Oct 2026 16:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:80ea72c4-1748-427e-9460-55a2cae5c181Tristan MorrisHey Ashwini, Unfortunately I can't access your attached image-- it appears to have included the name of the image but not the image itself. A quick summary of how LMK1C1102A output behavior works-- if the output enable (1G) is pulled high, then the outputs will match the CLKIN pin, with some amount of propagation delay. On one single transition on CLKIN, you should see that single transition appear as a rising or falling edge on the output of the device, after the propagation delay. As an example, if you give the part a rising transition on CLKIN, you should see the output produce a rising edge. Thank you, Tristanhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1691983/lmx2594-lmx2594-ramp-limit-low-and-high/6519963Fri, 23 Oct 2026 16:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b9732a5e-dc84-496e-93d3-a38cc23613cdNoel FungHi there, Would you provide a drawing on the ramp waveform that you want to implement?https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692267/lmk1c1106-lmk1c1106-lmkdb1104-lmkdb1102-olb-fileFri, 23 Oct 2026 12:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f7ca6fbc-55a2-4aa3-b86c-8dc7051e5b1bSean Liao (Yu-Sheng)Part Number: LMK1C1106 Other Parts Discussed in Thread: LMKDB1104 , LMKDB1102 , Hi all, Pls provide LMK1C1106 / LMKDB1104 / LMKDB1102 OLB file to build symbol, thanks a lot!Wired networkingLMKDB1104LMKDB1102LMK1C1106https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692260/lmx2595-current-consumptionFri, 23 Oct 2026 11:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:675d9cd1-5970-4b0c-a69e-417eaa5ca8e5Gone AkhilPart Number: LMX2595 We are using the LMX2595 PLL synthesizer configured to generate a 16 GHz output frequency. After programming the device and achieving frequency lock, the measured current consumption is approximately 458 mA at a 3.3 V supply , which is higher than expected based on the datasheet specifications. Could you please help us identify the possible causes of this excessive current consumption and suggest ways to reduce it? Specifically, we would appreciate your guidance on the following points: What are the possible reasons for the LMX2595 drawing approximately 458 mA at a 16 GHz output frequency? Which register settings affect the device's current consumption? Are there any recommended register configurations or settings that could help reduce current consumption without compromising frequency lock, output power, or phase-noise performance?LMX2595TICSPRO-SWAerospace & Defensehttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1677428/lmk05318b-unexpected-1pps-phase-offset-between-priref-and-out7/6519672Fri, 23 Oct 2026 11:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:74aebae1-41c1-4d2b-b76f-88066762cef1Serizawa ToshitakaHellow, We have conducted several investigations regarding this issue. When we tested using another test board within our company, it appeared that the phase offset in the 1PPS signal is related to the shift in the OUT7 1PPS output timing following a SOFT_RESET. Could you advise on the possible factors that may contribute to this phenomenon? For your reference, please see the attached waveforms below. (1,2: Test Board, 3: LMK05318BEVM) Phase offset: about -70 ms Phase offset: about 500 ms Phase offset: about 0 s (EVM) Furthermore, with the test board showing about a 500 ms offset, we changed the frequency of the XO (19.2 MHz) from around -300 ppb to 2000 ppb and conducted SOFT RESET, but observed no change in the phase offset.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692118/lmk1c1102a-lmk1c1102adqfr-output-enable-of-this-icFri, 23 Oct 2026 05:48:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6478cc51-2739-4e14-ac37-7129e46edbfbAshwini Kumari MPart Number: LMK1C1102A We would like to understand the output-enable behavior of the LMK1C1102ADQFR when a transition occurs at the CLKIN pin (pink waveform), with the 1G pin held permanently HIGH. Specifically, how do the outputs respond to this input transition?LMK1C1102ATest & Measurementhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692081/lmk05318b-request-for-certificate-of-volatility-for-lmk05318brgzFri, 23 Oct 2026 02:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:98984a6e-1096-42c8-92c2-26b901403b58Wang LiPart Number: LMK05318B To whom it may concern: We request a Certificate of Volatility for the unit/product supplied by Texas Instruments as detailed below, as part of one of my program’s sanitization procedures: Product/Model: CLOCK GENERATOR, LOW JITTER, 8 OUTPUT Unit ID/Serial: LMK05318BRGZ Please issue a certificate that: Describes the unit’s volatile/non-volatile memory characteristics and data retention behavior Identifies the unit by model and serial number States the certificate’s validity through Is signed by an authorized representative and provided on company letterhead (PDF). If available, please include supporting test reports or technical datasheets. Kindly confirm receipt and advise the expected issuance date. thanks.LMK05318Bhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1691941/cdcun1208lp-clock-buffer-timing-appears-to-be-not-met-by-my-design-adding-capacitors-didn-t-help-other-ideas/6519142Fri, 23 Oct 2026 00:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b759ac78-b62c-4c93-94b0-23b0bb263d6eTristan MorrisHey Clark, The current on VDD should be around 18mA, with the current on VDDO1234 around 36mA. Could you tell me a bit more about your application? It sounds like you want the clock to wait to start until after the 0.8V rail comes up, but I don't see that rail in the schematic snippet you've shared. Since it's not connected to the part, I would assume you are waiting on the part's delay for it to start oscillating an output. I think reducing the VDD to a 1uF filter would be a good debug step to see if then VDD comes up before or at the same time as the VDDO pins. Thank you, Tristanhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1691983/lmx2594-lmx2594-ramp-limit-low-and-high/6519131Fri, 23 Oct 2026 00:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f9f9fc94-00b5-4774-a58d-d32292bf3c88Brian MaceHello Jim, Let me check with our design team for this part, and will get back to you later this week. Best, Brianhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1691918/lmk04832-lmk04832-debugging-issue/6519129Fri, 23 Oct 2026 00:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:030e9571-f015-48df-b1ca-ac64b21cb19aBrian MaceHello Ian, For this, we will need to set up a test bench to try to replicate this issue. We will get back to you later this week with an update. Best, Brianhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1691608/lmk05028evm-lmk05028evm-config-as-a-100-mhz-to-10-100-mhz-fanout/6519047Thu, 22 Oct 2026 21:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:19b832bd-a417-464b-96bf-a2b346b91781Jaryd DukesHi Kevin, Here is a .tcs file with the frequency plan you're looking for; let me know if you have any issues with the config. lmk05028EVM-config.tcs Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1691941/cdcun1208lp-clock-buffer-timing-appears-to-be-not-met-by-my-design-adding-capacitors-didn-t-help-other-ideas/6518937Thu, 22 Oct 2026 19:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6e311fe3-82df-4a90-a361-3396279e72c5Clark Tollersonhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1691941/cdcun1208lp-clock-buffer-timing-appears-to-be-not-met-by-my-design-adding-capacitors-didn-t-help-other-ideas/6518933Thu, 22 Oct 2026 19:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4f125d75-2c38-4caf-8a11-eb1cd434ede7Clark TollersonThe TI CDCUN1208 Clock buffer provides the reference clock to a Broadcom Phy. Broadcom requires that the ref clock on power up not be present until the last supply is up. In my design 2.5V and 1.8V come up first, then 0.8V. On the 2.5V is the rail to both VDD and VDD1234 and I saw a requirement that VDD had to come up either before or at the same time as VDDO1,2,3,4. I thought I made an oscope capture where VDD01,2,3,4 came up before Vdd. Now when I capture it today I see ch 1 and ch 2 appear correct for VDD and VDD1234. VD1234 appears to be delayed some. I have a ferrite bead and 10uf cap and other smaller caps on Vdd but on the VDDO1234 I have only a 1uf and the same smaller caps and ferrite bead. It seems for the same current the VDDO1234 would come up first and I would not meet TI's requirement. Can you tell me the current on VDD and VDD1234 (for 4 LVDS outputs)? Is a 10uf good on VDD and a 1uf on VDDO1234? Could I reduce VDD to a 1uF?https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1691608/lmk05028evm-lmk05028evm-config-as-a-100-mhz-to-10-100-mhz-fanout/6518861Thu, 22 Oct 2026 18:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0a8cae9d-e788-40c4-bdb2-7d386033ec74Kevin BattlesHi Jaryd, would you be able to provide a .tcs config file for the LMK05028EVM that I could load to get the configuration I am looking for above without the 1 PPS TTL integration?