https://e2e.ti.com/support/clock-timing-group/clock-and-timing/ Products covered in this section are Clock Generation & Distribution, Memory Interface, Registers, Real Time Clocks and Timers. en-USTelligent Community 13https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1693270/lmk6l-q1-frequency-stability-including-reflow-processWed, 28 Oct 2026 06:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:36e3bcf9-b5b4-4ac1-9295-62843886ebc6Yoshiki OchiPart Number: LMK6L-Q1 Hi team, Does "Total frequency stability" includes frequency shift by "reflow process" as shown in https://www.ti.com/lit/an/spraby1a/spraby1a.pdf, figure 3? In addition, consdieirng frequency stability wiwith reflow process, over temp, and 10-year aging, how do we calculate ppm? Regards, OchiLMK6L-Q1https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692118/lmk1c1102a-lmk1c1102adqfr-output-enable-of-this-ic/6523310Wed, 28 Oct 2026 06:20:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e2251c12-1e7e-4762-a7a7-5e8dc56069d8Ashwini Kumari MThank youhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1688309/lmk03001-the-value-and-variation-of-the-internal-pull-up-resistor/6523242Wed, 28 Oct 2026 04:59:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:70fd8de8-aa71-422b-9cb1-75eb3bde663fuser6004480Hi Sandra, Could you please tell us, if there any update on the situation?https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692923/cdcs503-oe-pin-behavior-and-impact-on-internal-pll/6523221Wed, 28 Oct 2026 04:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9cd46cd5-5c48-4c23-99ae-d11e05181dd0Ryu YamashitaHi Sandra, Thank you for your reply. I have a few more questions. Is it okay to change FS while OE is Low and there is an input signal on IN? Also, how long does it take for the PLL to stabilize after changing FS? (How long should we wait after changing FS before setting OE High?) Best Regards, Ryu.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692931/lmk00301-clock-synchronization-scheme/6523060Wed, 28 Oct 2026 00:19:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d2e8657e-62f8-4c58-a489-9507b7e440faTristan MorrisHey Colin, I'm taking a look at these specs, I should have an update for you tomorrow. Thank you, Tristanhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692940/lmk00338-inquiry-regarding-a-clock-buffer-recommendation/6523057Wed, 28 Oct 2026 00:18:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5673de17-5f10-4118-a0c9-a98dd446267aTristan MorrisHey JH, What stage of design is your customer in? For PCIe, if LP-HCSL is accepted we can recommend the LMKDB family of devices, in this case LMKDB1108 (1:8 LP-HCSL Buffer). These are PCIe Gen7 compliant buffers that require no output termination. If they require HCSL exclusively, please let me know and I can explore more options for you. Thank you, Tristanhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1693170/cdcdb803-smbus-to-disable-selected-clock-outputTue, 27 Oct 2026 23:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e6ff0b56-ecbf-419c-9378-03748c6307e7RANGA SWAMY KPart Number: CDCDB803 Hello, How and what registers to be used to disable selected clock outputs of CDCDB803RSLR part using SMBUS when OE is pulled to ground and CKPWRGD_PD is tied to high logic. Table "Table 7-1. OE[7:0]# Functionality " is not clear what registers to be used to disable selected clock outputs.CDCDB803https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692923/cdcs503-oe-pin-behavior-and-impact-on-internal-pll/6522930Tue, 27 Oct 2026 21:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1f0451a1-2917-4ffe-845b-5a4185dd423aSandra SabaHi Ryu, Yes, the OE only controls the output state. OE state has no effect on the PLL status. In normal operation the output is muted until the PLL is stable, locked and the clock is ready. As long as CDCS503 has a valid clock input and PLL is locked, the device will continue operating as expected. Best, Sandrahttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692527/cdcvf2505-question-regarding-cdcvf2505-ibis-model/6522920Tue, 27 Oct 2026 21:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0d9ceb20-9e9b-4ca3-8263-6320bcde197fTristan MorrisHey Ryoya, Based on the linked apps note, the IBIS model should include the 25ohm on-chip series damping resistors as it is a part of the output driver. Thank you, Tristan https://www.ti.com/lit/an/scaa045a/scaa045a.pdfhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1693120/lmkdb1204-the-lmkdb1204rexr-technology-issue/6522810Tue, 27 Oct 2026 18:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:eec6eea4-5e73-4977-b240-a95d96241ff5Tristan MorrisHey Zhang, What you describe sounds correct, but just to make sure we are on the same page: Assuming both CPU0 and CPU1 are your input signals, with CPU0_REFCLK attached to the CLKIN0 pins, and CPU1_REFCLK attached to the CLKIN1 pins. Bank 0 is OUT0-1, Bank 1 is OUT2-3. CLKIN_SEL = LOW; CPU0_REFCLK(CLKIN0) -> Bank 0 and Bank 1; CPU1_REFCLK (CLKIN1) not buffered out CLKIN_SEL = MID; CPU0_REFCLK(CLKIN0) -> Bank 0; CPU1_REFCLK(CLKIN1) -> Bank 1 CLKIN_SEL = HIGH; CPU0_REFCLK(CLKIN0) not buffered out; CPU1_REFCLK(CLKIN1) -> Bank 0 and Bank 1 The only changes made from what you stated was the terminology to clarify in our datasheets terms, identifying bank 0 and bank 1. Thank you, Tristanhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692860/lmkdb1104-threshold-voltages/6522768Tue, 27 Oct 2026 18:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9b2d3013-9d77-492a-b1f7-835e69d9efcfTristan MorrisHey Prince, Refer to the table below. This is available in our datasheet for your reference as well, near the end of section 6.5, Electrical Characteristics, p. 32. Thank you, Tristanhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1693120/lmkdb1204-the-lmkdb1204rexr-technology-issueTue, 27 Oct 2026 17:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:33b9a93b-a211-4a12-9bf4-33a8a7a29cb6Zhang LiangPart Number: LMKDB1204 Hi, LMKDB1204REXR is a 2-in-1 4-out CLK buffer, with CLKN_SEL_tri controlling the channel switch. Does that mean that the input supports same/different source REFCLK input, and then through the selection of CLKN_SEL_tri, the CPU REFCLK&PCIE and SSD CLK&PCIE achieve the same source effect. For example: input source CPU0 REFCLK for IN0, CPU0 REFCLK for IN1, CLKN_SEL_tri selects low level; Input source CPU0 REFCLK for IN0, CPU1 REFCLK for IN1, CLKN_SEL_tri select medium level; Input source CPU1 REFCLK for IN0, CPU1 REFCLK for IN1, CLKN_SEL_tri select high level;Industrial AutomationLMKDB1204https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692760/lmk3h2108-lmk3h2108-having-custom-vcm/6522683Tue, 27 Oct 2026 17:03:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b5c83733-52dc-4a4b-9c8d-9db3023dc434Sandra SabaHi Andrei, sent you an email. closing out this ticket to continue offline Best, Sandrahttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1689583/lmkdb1104-the-voltage-issue-for-lmkdb1104z100rexr/6522237Tue, 27 Oct 2026 10:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:909bd84d-d4db-49c3-bc9a-fb50f31df940Zhang LiangHi Michael, At the input end of the clock chip, there is an AC coupling capacitor on the P/N line, and the resistance between PN is 100 ohms. At the output end, the resistance connected to the downstream chip end is 200 ohms, and the level is HCSL, which is the Demo design requirement of the downstream chip. The clock frequency is 156.25 MHz. What we want to know is, why does the CLK (AC capacitor at the rear end) at the input end rise by about 400 mV relative to the starting point? Is this a normal situation for Ti's clock chip? And why does Renesas not have this difference?https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692940/lmk00338-inquiry-regarding-a-clock-buffer-recommendationTue, 27 Oct 2026 08:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3f0b96fa-0909-402c-817a-930fe3f2b59bJH ShinPart Number: LMK00338 Other Parts Discussed in Thread: LMKDB1108 Hello, My customer is looking for a clock buffer that supports the following conditions. - Input clock : 100MHz Oscillator - Output clock : 100MHz HCSL - Number of output : 8 CH - Output clock characteristics: Reference clock input for PCIe Gen3 interface devices(Refer to the table below) Could you please recommend the most suitable clock buffer from TI’s product lineup? Thank you. JHLMKDB1108lmk00338https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692931/lmk00301-clock-synchronization-schemeTue, 27 Oct 2026 07:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0fdfaf0b-bd2e-44c7-ad73-ff87ab25705eColin ChenPart Number: LMK00301 Dear Experts, Recently, a client has a project that requires the use of LMK00301SQE/NOPB and LMK00105SQ/NOPB for clock synchronization among multiple devices. The specific connection diagram is as follows: DSP requirements for input clock specifications: (1) Level range: 1.26V-1.8V (2) Required duty cycle range: 48%-52% (3) The frequency deviation is preferably controlled within 10 ppm (4) The clock frequency deviation of DSP among multiple service boards should be minimized The customer currently has the following application-related questions that require consultation, and hopes to receive answers from experts. 1. After cascading LMK00301SQE, how are the device tPD and P2P skew superimposed? According to this scheme, what is the total skew upper limit of the entire clock chain? Will the channel skew and duty cycle distortion of LMK00105SQ input and output itself affect the duty cycle specifications of DSP? 2. Is there any recommended differential impedance, differential pair length tolerance, and equal length constraint for clock routing between different service boards for cross-backplane LVPECL transmission? 3. Is there a recommended configuration for LMK00105SQ power supply filtering, specifically a coupling scheme for LVPECL input and LVCMOS output? Does the 1.8V LVCMOS output terminal require series resistance matching to ensure that the output level falls within the DSP's required range. 4. The input and output of LMK00105SQ belong to cross-power domain conversion. Does the chip itself have power-on timing requirements? If the buffer is powered on earlier than the DSP, is there a risk of reverse leakage in the 1.8V clock output pin of LMK00105SQ when the DSP power supply is not powered on? Thank youbuilding automationLMK00301https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692923/cdcs503-oe-pin-behavior-and-impact-on-internal-pllTue, 27 Oct 2026 07:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8b08d9ba-67fc-4a37-bc39-c9d3b781cd2cRyu YamashitaPart Number: CDCS503 Hi team, Background: We understand that the OE pin of CDCS503 controls only the clock output state. The datasheet shows OUT becomes 3-state when OE is Low, while the internal PLL processes the input clock. Questions: Can you confirm that changing OE High/Low does not stop, reset, re-lock, or otherwise affect the internal PLL operation? While OE is Low, does the internal PLL continue operating normally/continuously with a valid input clock? After OE changes from Low to High, is OUT simply enabled from the already-running PLL, without a new PLL lock sequence? Best Regards, Ryu.Industrial AutomationCDCS503https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692760/lmk3h2108-lmk3h2108-having-custom-vcm/6522042Tue, 27 Oct 2026 07:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3221dced-9560-4eb1-92a0-d6e9124ccb4aAndrei PopescuHow to send private messages? We noticed that this discussion is not private as it supposed to be. Please use our email to contact as, this is urgent.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1692860/lmkdb1104-threshold-voltagesTue, 27 Oct 2026 05:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8d72db21-a972-417c-80e9-788c321b3e14PRINCE GOLAPart Number: LMKDB1104 We are planning to use LMKDB1104Z85REXR in our new development project. So we require Voltage level threshold like Vih, Vil, Voh, Vol for the pins ^vSADR1_tri, ^vSADR0_triv, SBI_EN, vPWRGD/PWRDN#, ^OE0#/vSHFT_LD#, ^OE1#/vSBI_IN, ^OE2#/vSBI_CLK, ^OE3#/vSBI_OUT, ^SLEWRATE_SEL, and LOS#. These are digital I/O pins.Wired networkingLMKDB1104https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1689583/lmkdb1104-the-voltage-issue-for-lmkdb1104z100rexr/6521710Mon, 26 Oct 2026 22:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fe4cc39c-36ce-4095-830e-7d391ef5ebeaMichael SrinivasanHi Zhang, Is there a reason you have a 200Ohm resistor between P and N? If the clock is HCSL they should only have 50Ohm terminations to GND. Thanks, Michael