https://e2e.ti.com/support/clock-timing-group/clock-and-timing/ Products covered in this section are Clock Generation & Distribution, Memory Interface, Registers, Real Time Clocks and Timers. en-USTelligent Community 13https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1642068/lmx1204-regarding-the-bom-of-the-lmx1204evm/6335498Wed, 06 May 2026 23:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7cb15d58-0c9d-4378-8c26-e723848e636fShuji IshiwataHi Thank you for your answer. Please tell me your recommend ferrite beads. Best Regards, Ishiwatahttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1643161/lmkdb1202-cascade-questionsWed, 06 May 2026 17:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c77a6745-1e1b-41fa-a987-961531c1511bAllan FanPart Number: LMKDB1202 Other Parts Discussed in Thread: LMKDB1204 Hi experts, Regarding the PCIe Gen6 RefClk: will it still function properly if it passes through 3 or 4 CLK buffers? Customer is considering LMKDB1204 and LMKDB1202. How should we estimate or evaluate the cumulative impact of cascading these buffers? Note that the specifications for the first buffer are currently unknown, as it depends on the specific motherboard design. BR, AllanLMKDB1204Data center & enterprise computingLMKDB1202https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1642907/lmk05318bevm-spikes-observed-in-the-phase-noise-of-100-mhz-output-from-lmk05318b-eval-board/6335107Wed, 06 May 2026 16:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cda91a2b-ccd8-45fa-9d51-094e6a60424dConnor LewisHi Suchitra, Thanks for the detailed summary here. Just to confirm, is the DPLL locked in the auto non-revertive phase noise plot? It's possible that the spurs are being introduced by the 48MHz XO reference, and when the DPLL locks the close-in noise is dominated by the 10MHz reference so these spurs effectively get filtered out when the DPLL is locked. To verify this, could you capture phase noise measurements of the 48MHz reference? Could you also please attach your .tcs configuration files? The .txt programming files are helpful but the .tcs files help me review fields in the wizard configuration (such as DPLL LBW) which aren't stored as simple register values.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1643157/lmk6b-samples-of-lmk6bpe625000fdlrWed, 06 May 2026 16:43:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:42bad2eb-f0d3-40a4-a1be-e14cc74f170fChih WongPart Number: LMK6B Dear, We can't find LMK6BPE625000FDLR online, could you contact us and arrange samples? Regards, ChihBroadband fixed line accessLMK6Bhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1642883/lmk04616-software-to-configure-lmk/6335053Wed, 06 May 2026 16:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6155e05d-dff6-4d41-90fb-64188256c1e9Noel FungHi There, Did the link take you to below webpage? https://www.ti.com/tool/TICSPRO-SWhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1643015/lmx2595evm-manual-ramping-pulse-count/6335035Wed, 06 May 2026 16:23:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2a815ae3-d911-4803-bf70-cded8c26e140Noel FungHi There, If the 1MHz step size is at VCO frequency and the ramp clock frequency is low (e.g. 10kHz), then 3520 ramp clocks are enough. Please note, there are multiple VCO calculations during the whole ramp period. Calibration may take more than 20µs, during this time interval, ramp clock is ignored. For example, if your ramp clock frequency is 1MHz, assume the calibration takes 10µs, 10 ramp clocks will be ignored during calibration. As a result, you need more ramp clocks than the theoretical number.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1643052/lmk61e07-request-for-ibis-model-for-lmk61e07-siat/6334979Wed, 06 May 2026 15:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:de4585e9-fea3-47fc-b250-7dd4735e5816Connor LewisHello, You can use the LMK61E2 IBIS model, found under the "Design tools & simulation" tab of the product page here: https://www.ti.com/product/LMK61E2#design-tools-simulation LMK61E2 and LMK62E07 have identical output drivers, so it should be suitable to use the LMK61E2 model for SI analysis. The main difference between these devices is that LMK61E07 uses a crystal with better frequency stability.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1643052/lmk61e07-request-for-ibis-model-for-lmk61e07-siatWed, 06 May 2026 12:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:16ee364f-5e42-48c1-bccd-20e0ddfa40cdkrish krishPart Number: LMK61E07 Other Parts Discussed in Thread: LMK61E2 , Dear TI, I need IBIS model for LMK61E07-SIAT to carryout SI analysis for custom board application. Request you to kindly provide the same.LMK61E2LMK61E07https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1638689/lmx2572-lmx2572-allowable-voltage-drop-during-inrush/6334517Wed, 06 May 2026 10:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:72d65858-29f9-4ff9-aa62-3bc6b0725bc3Andrew WilliamsHi Noel, I am just following up with regards to my previous question. Have you been able to have a look at it or can you provide a rough date at which you may be able to get back to me? This would help clarify our project timeline on resolving this issue.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1643015/lmx2595evm-manual-ramping-pulse-countWed, 06 May 2026 10:44:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:81b03822-f366-4867-9453-24d2d4b55058Akshay SugandhiPart Number: LMX2595EVM I am performing manual ramping, from 480 MHz to 700 MHz and its equivalent fvco is 7860 MHz and 11200 MHz respectively. and trying to ramp with step size of 1 MHz. Below are the calculations made as per TICs pro software channel divider 16 Ramp Input Clock 0 2684355 Ramp Input Clock 1 1071057469 Ramp Limit high 590558003.2 Ramp Limit Low 8589934591. My doubt is that how do I calculate the number of ramp clock pulses needed here ? If I use ramp pulse count = (fvc stop frequnecy - fvco start frequency)/step size I observed that its just ramping from 485MHz to 521MHz, even though we are sending 3520 pulse pulse count = (11200-7680)/1 = 3520 pulses Could you please explain why is this happening ? but if I send double (3520*2) pulses I get full range (480 to 700MHz).LMX2595EVMhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1642907/lmk05318bevm-spikes-observed-in-the-phase-noise-of-100-mhz-output-from-lmk05318b-eval-boardWed, 06 May 2026 07:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f235cdc7-b4fd-4ea0-8f90-f0f6048afc1bSuchitra RamamoorthyPart Number: LMK05318BEVM Other Parts Discussed in Thread: LMK05318B Hello, We are using the LMK05318B eval board to generate 100 MHz from OUT0_P and OUT7_P of LMK05318B. The eval board is operated on a +5V supply, which is connected to Vin1. 10 MHz OCXO(+2dBm) is given at PRIREF_P and 48 MHZ OCXO (0dBm) is given at XO_P connectors on the eval board respectively. The OUT0_P and OUT7_P are enabled to give 100 MHz. When the reference input switching mode is set as Auto Non-Revertive, we get a 100MHz output with a clean phase noise with no spikes in the phase noise plot. The image is attached below. Whereas, when we set the switching mode to manual holdover, we observe spikes in the phase noise of 100 MHz. The image is also attached below. The eval board is being programmed using TICSPro GUI. The programming files of both cases are attached below. 100 MHz auto non revertive.txt 100 MHz manual holdover.txt We want to get a clean phase noise in the manual holdover mode as well. Any insights into this issue would be greatly helpful. Regards, Suchitra Ramamoorthy.LMK05318BEVMLMK05318Bhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1642883/lmk04616-software-to-configure-lmkWed, 06 May 2026 07:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:60f526c1-5426-4cde-9efa-3da46d1000a4Mike MeuryPart Number: LMK04616 Hi, I want to use a GUI interface to configure a LMK04616ZCR present on homemade board through an SPI interface. I am just requesting a usable link to download TICSPRO SW correctly because the link on the website lead me to a bad request page. Thanks for your help.LMK04616TICSPRO-SWhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1642858/cdcbt1001-cdcbt1001-application-for-50ohm-termination-loadWed, 06 May 2026 06:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f07f77b9-bbd1-4e2d-bf4b-4a26007f4f33Youwei LinPart Number: CDCBT1001 Hi TI team, We are using CDCBT1001 with VDD_OUT = 2.5V to drive a single-ended 10MHz clock at 50ohm load as picture below. Vout is (2.5)(34)/(34+50)=1.5V due to voltage divider and Iout is 2.5V/(34+50)=30mA which is below maximum continuous output current 50mA, but since datasheet does not list out the recommended operating condition for VDD_OUT=2.5V, we would like to know if this 30mA would cause damage to the device and shorten the device lifetime or it is acceptable for the device under this kind of operating conditon? BTW, Is there other recommended buffer IC that is able to drive a 50ohm load under recommended operating condition...? Thanks, YWCDCBT1001Data center & enterprise computinghttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1642346/lmx2594-sync-function/6334075Wed, 06 May 2026 05:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5e468d2b-a820-4fd4-ad4d-981beb3d966fyaacov shoefthanks Noel, my reason for doing the timing is because I need also cat.3 cases. my question is : if multiple pulses (let say 5 pulses) in spaces of 10ns (the clock period) can damage the sync process? and another question: is the ambiguity of sometimes 0 degrees and sometimes 180 degrees an expected result or the sync function should yield always 0 degrees?https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1638587/lmk04828-multi-board-mts-synchronization-scheme-for-zynq-ultrascale-rfsoc-49dr-gen-3-and-lmk04828/6334057Wed, 06 May 2026 05:20:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fe088114-3a4f-4280-832d-bbd9466bf9fePratiksha Halijwale1Hi Michael, Oscin frequency is 100 MHz. I am generating 225MHz as ref and 5.625MHz as sysref frequency. Can I configure it in zero delay mode with sysref as feedback frequency without changing input reference frequency of 100MHz? Also, if I don't use zero delay mode then applying a sync pulse to sync pin of lmk will align the clocks on multiple boards? Thanks, Pratikshahttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1642622/tms320f28335-q1-tms320f28335-q1-ic-interface-with-crystal-via-series-damping-resistor-to-reduce-to-within-drive-level-of-crystal/6333974Wed, 06 May 2026 04:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ced8836f-c3aa-4325-b586-d607cc17eb05MatthewPateTo your initial questions; the Rd needs to be placed on the X2 net, as this is what is driving the XTAL, so Rd here will reduce the current that the XTAL sees. I don't believe that placement on the X1 net will have any effect on the damping. X1 itself is a high impedance node. Based on other E2E posts I believe that the oscillator circuit will have a maximum of 100uW drive level. If your crystal can handle this amount we can bypass the Rd altogether and remove it from X1 circuit. Else we do need a Rd, and it should be moved over to X2 per the above. No, the internal oscillator doesn't have a damping resistor built in. There is a Rf internally, so that doesn't need to be added to the design. If needed I'd start with a Rd on the smaller side to not limit the drive current as much, so that the XTAL starts up quickly. Again if the XTAL can take up to 100uW, then there's no need for a Rd at all. Best Matthewhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1641366/lmx2594-lmx2594-no-assist-vco-calibration-fails-to-lock-at--30-c-some-chips-lock-while-others-don-t-on-the-same-board/6333843Wed, 06 May 2026 01:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9d854a62-4b07-473a-8958-8514c543e981MarkHi, Sorry for taking so long to reply. The TCXO output signal is sinewave of 7dBm with 50-ohm loaded and its output harmonics level is <-35dBc. Its connections is shown in the figure.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1642488/lmk3h0102-question-about-lp-hcsl-clock-output-characteristics-table-of-lmk3h0102/6333818Wed, 06 May 2026 00:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:01ff4e35-29b3-4c27-afb7-508d094910f4Jaryd DukesHi Tim, The VOH for LP-HCSL is defined by a single-ended output with respect to ground. V_A in the image represents the single-ended VOH seen in the datasheet, while V_B is the output low voltage (V_min) Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1641735/lmk04828-design-review/6333802Tue, 05 May 2026 23:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:423f910e-e81c-4643-9677-65f88a2aaa7fMichael SrinivasanHI JH, The configurations look good! Just make sure that CLKin1 is configured to send the input to the FB Mux. Thanks, Michaelhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1641837/lmk04832evm-lmp7731mf-nopb-u6-on-lmk04832-evm/6333745Tue, 05 May 2026 22:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f93b5853-05e1-4a7f-a52e-3233b4cb874bBH KIMThere is no problem with on-board Crystek VCXO. We are testing with Q-tech VCXO via external SMA. As I have posted my previous problem that LMK04832 did not create the PLL1 lock with Q-tech 122.88MHz VCXO and 10Mhz Reference clock. ( https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1613987/lmk04832-lmk04832-lock-issue-due-to-vcxo-s-harmonics/6224926?tisearch=e2e-sitesearch&keymatch=%2520user%253A416399# ) (PLL1 lock has well operated with Crystek VCXO) So, we are looking for a way to lock PLL1 when using the Q-tech VCXO(Q-tech VCXO's input impedance is 51kohm). Are you saying the amp on the EVM can't be used as an impedance buffer? If I want to use it as one, do I need to modify the board?