https://e2e.ti.com/support/clock-timing-group/clock-and-timing/ Products covered in this section are Clock Generation & Distribution, Memory Interface, Registers, Real Time Clocks and Timers. en-USTelligent Community 13https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1684221/cdce6214-pll-not-indicating-locked-status/6501017Sun, 04 Oct 2026 06:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d49e831e-151b-4de6-9810-9b329496d22fRishabh JainGlad I could help Gian. Regards, Rishabhhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1683207/lsf0102-lsf0102dctr-severe-signal-distortion-at-12-5-mhz/6500862Fri, 02 Oct 2026 21:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:dd9a0daf-9273-4e14-9c0f-3b0b6512c2c0Jason TrinhHi Shay, Sorry for the delay on this one. I will respond early next week. In the meantime, has there been any updates? Regards, Jasonhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1677428/lmk05318b-unexpected-1pps-phase-offset-between-priref-and-out7/6500859Fri, 02 Oct 2026 21:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c8a0402c-5456-4158-acf2-f1fc0dcb51c6Octo HalsemaDear hidetaka, Maybe your XO frequency is drifting during first minutes. Do you use an OCXO? I was able to reproduce similar behavior. Custom board, LMK05318B, XO=24.576MHz OCXO, 1PPS reference. First PPS pulse at out7 within about 10's of ns. Second and following PPS pulses with 67.2 ms offset. Solid at 67.2ms. DPLL freq+phase locked. How to reproduce at least 5 times: Custom board (hot OCXO) power interrupted for 30 seconds to let the OCXO cool down several degrees. PPS from GNSS continues with standby-power. My thoughts: After PRIREF validation the out7 unmuted and out7 divider is reset by the PRIREF pulse to get deterministic phase. The OCXO output frequency is not stable within the short ref validation period of 6.4 seconds. Still heating up. I believe that the (quasi) ZDM captures the PPS while rising/falling XO frequency. The LMK05318B has a ZDM implementation that works under certain conditions. With hot OCXO the phase was repeatable in the <50ns range. A controller soft-resets the LMK05318B after reaching stable working temperature or 5 minutes timeout period. Regards, Octohttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1686698/lmh1982-lmh1982-reset-recovery-time/6500688Fri, 02 Oct 2026 18:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:595a8f31-3597-4518-bb24-d163784acbb5Sandra SabaHi, According to the datasheet you need to ensure that the I2C_Enable\ = 0 to enable I2C communication. Please reference below snippet from the datasheet If youre referencing the RESET\ pin, to reset the device toggle it low for at least 10uS and then set it high. Please reference below snippet from datasheet Best, Sandrahttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1686335/lmk5b33216-tics-pro/6500669Fri, 02 Oct 2026 17:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:54cdf96e-4f3b-47e6-8264-0c9c415f94e1Jaryd DukesHi Cal, Python 3.11.5 is built into the TICS Pro installer, but it can be turned off in TICS Pro so it never activates. On startup, TICS Pro checks the settings.ini file for a [PYTHON] section. As a workaround, if DISABLE=TRUE in this section, the embedded python scope (used for the PCIe jitter calculation tool) is disabled. Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1685957/lmk04906-pll1-loss-of-lock-when-multiple-clocks-present-on-clkinx-inputs/6500471Fri, 02 Oct 2026 14:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:04b54128-30ae-4b98-99b0-321a89305d3bRoy IllingworthMichael, Pretty sure we have monitored with LD_MUX = 1 (need to re-run to be sure - that will be next week), that is why we know it is PLL1. Not sure we have ever tried LD_MUX=2, normally LD_MUX is set to 3. Even if it were PLL2 and not PLL1 it is still an issue. We have tried both auto mode and manual mode. In auto mode with EN_Clkin2=0 (not the clock we are monitoring) we do see an improvement but it is still not as stable (i.e. we still see loss of lock, just less frequently) as with the clock absent. Circuit enclosed : : As for Clkin_Select we have set to both manual and auto. But here is a dump of the registers: | Addr | DATA field | 32-bit word | |---|---|---| | R0 | 0x000A03C | 0x00140780 | | R1 | 0x400A03C | 0x80140781 | | R2 | 0x400A03C | 0x80140782 | | R3 | 0x400A03C | 0x80140783 | | R4 | 0x400B0F0 | 0x80161E04 | | R5 | 0x400B0F0 | 0x80161E05 | | R6 | 0x0660000 | 0x0CC00006 | | R7 | 0x0000000 | 0x00000007 | | R8 | 0x0606000 | 0x0C0C0008 | | R9 | 0x2AAAAAA | 0x55555549 | | R10 | 0x10A2D2A | 0x2145A54A | | R11 | 0x0000180 | 0x0000300B | | R12 | 0x0D9600C | 0x1B2C018C | | R13 | 0x1D88487 | 0x3B1090ED | | R14 | 0x4998000 | 0x9330000E | | R15 | 0x2003DEE | 0x4007BDCF | | R16 | 0x0000000 | 0x00000010 | | R24 | 0x0001B18 | 0x00036318 | | R25 | 0x7106739 | 0xE20CE739 | | R26 | 0x5406B5A | 0xA80D6B5A | | R27 | 0x0E00008 | 0x1C00011B | | R28 | 0x0010050 | 0x00200A1C | | R29 | 0x008000C | 0x0100019D | | R30 | 0x008000C | 0x0100019E | Thx, Royhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1684221/cdce6214-pll-not-indicating-locked-status/6500409Fri, 02 Oct 2026 11:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:30df2945-f557-4aac-a59e-c3d2e4da6569Gian-Luca BrazerolHi Rishabh, I think that was it, I now get the PLL-Locked status from the register reading. Thank you very much for your support. Regards, Gian-Lucahttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1677428/lmk05318b-unexpected-1pps-phase-offset-between-priref-and-out7/6500336Fri, 02 Oct 2026 08:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ec24701d-4ce6-4ba8-b243-7ffec78aaf23hidetaka hayakawaThank you for your response. I have taken over this matter from Serizawa. When I checked register R148 read from the EEPROM, I found that it was set to 0x86 . I tried changing this setting to values in the range of approximately 0x70 to 0xA0 , where BAW LOCK converges, but this had no effect on the issue in which a 26-microsecond offset is inserted. I also measured the voltage on the LF1 pin and found it to be approximately 1.13 V, which appears to be within the expected range. Attached are the measured waveforms on the PRIREF and OUT7 pins when RESET_SW was executed by changing register 0x0C from 0x9B to 0x1B . In the video, register 0x50 , bit 7 (BAW LOCK), remains 0b1 throughout. Register 0xA8 , bit 1 (DPLL LOCK), transitions to 0b1 at approximately 0:40. Register 0xA8 , bit 2 (DPLL PHASE LOCK), remains 0b0 throughout the video; however, it changes to 0b1 after the video ends. In addition, the phase relationship between PRIREF and OUT7 does not change. e2e.ti.com/.../PRIREF_2800_BLUE_2900_toOUT7_2800_RED_2900_.mp4https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1686698/lmh1982-lmh1982-reset-recovery-timeFri, 02 Oct 2026 05:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c295cbff-d133-401a-a42c-f348df429d40Tetsuo TakadaPart Number: LMH1982 How much wait time is required between deasserting the LMH1982 reset and starting the I2C configuration?Industrial AutomationLMH1982https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1686686/lmx2572lp-oscin-configurationFri, 02 Oct 2026 03:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7078544e-f6ff-4611-9b52-530e0e1601e1Peter hengPart Number: LMX2572LP hello,i found the reference circuit of the LMX2572LP from the EVM schematic. i plan to use cmos oscillator SXO32C3B481-100.000M(Suntsu) parts. therefore i would like to know do i need to have R35=51ohm connected before the oscillator as shown below. Pls feel free to provide any other alternative Oscin type with better performance. Thank you.Wireless InfrastructureLMX2572LPhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1686679/lmk1d1208evm-proper-input-and-output-terminations-of-lmk1d1204-with-single-ended-sine-wave-inputFri, 02 Oct 2026 03:18:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9167ef6a-b2b2-4ed6-b4ab-983a1cfa9327Noman ParachaPart Number: LMK1D1208EVM Other Parts Discussed in Thread: LMX2592 , LMK1D1204 Hi, I am using LMK1D1204 (Vcc = 3.3V) to convert a single-ended 10 MHz sine wave from a signal generator and produce four LVDS outputs that are fed to OSCin pins of four LMX2592 synthesizer ICs. Per suggestion in LMK1D1208EVM user guide, I made the following modifications on the input side: The shunt 50 ohms near J3 connector was not mentioned in the user guide, I added it there so I can get the correct bias voltage at the unused input pins. After this addition, I measure 1.65 V on + and - pins of IN0 input, which I believe is correct. Do these changes look correct? On the output side, i made the following edits so I can connect it to the OSCin+/- pins of LMX2592. The reason for removing the AC coupling caps (C12 and C14) is that there are AC coupling caps close to LMX2592 OSCin +/- of its eval board. Is this the right thing to do and does this setup look correct to you? The reason, I am asking all these questions is that I am getting spurs at 6KHz offset at the output of the synthesizer that were not there when I use the on-board TCXO on LMX2592 eval board. See pictures below Can you help me solve this problem? I have really been strugling with it for the last two weeks and any help will be greatly appreciated. Thanks, NomanLMX2592LMK1D1208EVMWired networkingLMK1D1204https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1685898/lmk1c1102-cpu-ufs-clk-1-05v-to-ufs-1-8v/6500169Fri, 02 Oct 2026 02:49:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:71b13ba1-4594-444f-8650-137ac786b399Jeff YANGHi Michael, Got it, thank you! Jeffhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1685582/lmx1205-lmx1205-sysrefreq-pin-vcm-biasing-requirement/6500121Fri, 02 Oct 2026 00:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9744b8fc-1f7d-491c-9055-139cee84d6e1Hori ShotaHi team, We are still waiting for your response. Is this device no longer supported? If so, could you please let us know its support status and whether there is a recommended replacement device? Best Regards, Shotahttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1685447/lmk03328-lmk03328-deterministic-phase-relationship-between-reference-bypass-27-mhz-and-pll-generated-74-25-mhz-outputs/6500115Fri, 02 Oct 2026 00:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7e0769e3-e3b9-4109-8fff-de50bdaaadafJaryd DukesHi Kyohei, Apologies for the delay and thanks for your patience. In bypass mode, the typical input-to-output propagation delay is 1ns for LVCMOS and 400ps for differential outputs. This defines the fixed phase offset between the reference and the bypassed output. Keep in mind the bypass outputs can only come from OUT4-7. The phase relationship between outputs of these two different frequencies will change constantly and continuously. Since the reference and the PLL output are phase related, their phase relationship is technically deterministic, but this value is not specified in the datasheet and would require testing to observe the relationship. The phase relationship is not guaranteed to be deterministic across power cycles. Output synchronization works by resetting all output dividers simultaneously, and since the bypass outputs do not pass through dividers, this cannot be used to guarantee the same phase relationship between these frequencies after each power cycle. With identical divider settings we spec a maximum 60ps output-output skew for LVDS/LVPECL/CML outputs and 100ps skew for HCSL/LVCMOS outputs. Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1686352/lmk03318-lmk03318-ac-lvds-output-skew-if-not-in-divider-value/6500104Fri, 02 Oct 2026 00:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9964cde7-a5c1-4196-931b-9282909187d3Brian MaceHi Li, Reading the ADC datasheet more, it seems like they are only specifying the skew between the rising edge of the CNV input and the closest rising edge of the CLK input. I think the added delay from the additional dividers will be minimal, but I will talk to my team to confirm, and for an approximate number. We will get back to you tomorrow with more details. Best, Brianhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1686352/lmk03318-lmk03318-ac-lvds-output-skew-if-not-in-divider-value/6500080Thu, 01 Oct 2026 23:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9571d02f-2a69-4de5-b8aa-07a77dc24d7cLi YangHi, Brian. the ADC I used is AD4880. from the LMK03318 datasheet, with sync function, seems like the skew would be about 1 VCO clock cycle.. can you please help clarify that?? ADC req: LMK03318 datasheet:https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1686352/lmk03318-lmk03318-ac-lvds-output-skew-if-not-in-divider-value/6500078Thu, 01 Oct 2026 23:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9066cb47-23fe-4c81-94a4-0d7bd8c173b9Brian MaceHello Li, I am little confused by your question. When running multiple clocks at different frequencies, the edges will by definition not be aligned. Can you share which ADC you are using? Best, Brianhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1685957/lmk04906-pll1-loss-of-lock-when-multiple-clocks-present-on-clkinx-inputs/6500015Thu, 01 Oct 2026 21:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f7f94829-198c-4afb-a5de-804d2156becfMichael SrinivasanHi Roy, A couple things I'd be curious to know: - Can you program LD_MUX to values of both 1 and 2? That way you can determine if this behavior is specific to one loop, or applies to both - Can you provide the loop filter topology you are using in each loop? That information, along with your PFD values would give me enough information to determine if the issue pertains to the loop filters - Can you readback the CLKin_SELECT_MODE field? Does this issue persist through manual clock selection and auto mode? Thanks, Michaelhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1686456/lmkdb1202-lmkdb1202-does-it-behave-as-lmkdb1204-with-all-registers-fixed-at-reset-default-values/6499999Thu, 01 Oct 2026 21:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ac3adaa0-855d-4052-8a8b-daa8af62f8f1Michael SrinivasanHi David, [quote userid="463532" url="~/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1686456/lmkdb1202-lmkdb1202-does-it-behave-as-lmkdb1204-with-all-registers-fixed-at-reset-default-values"]Given the above, is it correct to assume that LMKDB1202 operates internally as if all the same registers listed in the LMKDB1204 register map (Section 9.1) are permanently fixed at their documented reset/default values (e.g., input termination disabled, AC-coupling disabled, default output amplitude, default slew rate option)?[/quote] This is correct. Thanks, Michaelhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1685898/lmk1c1102-cpu-ufs-clk-1-05v-to-ufs-1-8v/6499994Thu, 01 Oct 2026 21:20:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4411d49e-98c3-48f6-8ed5-ab6aef846a0dMichael SrinivasanHi Jeff, Rather than incorporate another active solution, you could input the 1.05V signal into the 1.8V-supplied LMK1C. The minimum required input swing is 0.72V at VDD = 1.8V, so all that would be required is AC-coupling the 1.05V signal and then biasing it to VDD/2. The output will then be 1.8V. Thanks, Michael