https://e2e.ti.com/support/clock-timing-group/clock-and-timing/ Products covered in this section are Clock Generation & Distribution, Memory Interface, Registers, Real Time Clocks and Timers. en-USTelligent Community 13https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1681369/lmk03001-handling-of-unused-pins/6481647Sat, 12 Sep 2026 08:20:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c01e10d5-e219-4114-87c9-e8df9d69728fuser6004480Hi Michael, Thank you for reply !https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1680251/lmk3h2104-how-to-generate-a-247-5-mhz-clock-signal/6481594Fri, 11 Sep 2026 23:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4f2b655c-6ede-451b-a36e-9585f419e831Jaryd DukesHi Zhang, Thank you for providing the context for your application and the system architecture. The LMK6x family does offer very low jitter from the BAW resonator, but will likely result in similar spurious issues as the LMK3H2104 since it also utilizes an FOD-based architecture to generate its outputs. For this specific application, I would suggest using the LMK61E2, as it is a PLL-based, 1-output, programmable oscillator with I2C capabilities and typical Fractional-N PLL 12kHz - 20MHz RMS jitter of 150fs (f ≥ 100MHz). The VCO tuning range of this device is 4.6 - 5.6GHz, meaning the fractional and integer boundary spurs can be minimized and will not be as impactful or numerous. Although this device does not have BAW, it should have comparable jitter and phase noise performance to the LMK3H2104. The LMK03318 is another potential PLL solution with a maximum 350fs RMS jitter in fractional PLL mode. The best-performing solution for this application would be the LMK5C22212A . This device utilizes a BAW VCO with typical 50fs RMS jitter at 245.76MHz. Because the BAW frequency is 2457.6MHz, this divides down evenly to your desired 245.76MHz frequency, which would eliminate any fractional and integer boundary spurs you see at the output. However this device does have 12 outputs and multiple APLLs and DPLLs, which may be a bit overkill for your application. Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1681136/lmk3h2104-how-to-use-buffer-function/6481568Fri, 11 Sep 2026 22:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:906f1d67-9b2b-43f5-8b02-bbf841ed834cJaryd DukesHi Bing, Can you try this configuration file instead? --> LMK3H2104_default_OUT0_IN0.tp2 Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1681463/cdce62002-alternative-recommendation-for-cdce62002/6481566Fri, 11 Sep 2026 22:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0c7e9928-c1c9-4431-b87c-40665abde8e2Sandra SabaHi Kyohei, Does the customer have any performance requirements? How many copies of each frequency do they need? For frequency planning, customer can also use clock tree architect for suggested clock tree design based on their requirements. There are no migration guides - customers can use datasheet, EVM guides and released documentation to set up the device. Best, Sandrahttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1681647/lmx2571-lmx2571-supply-current-and-output-buffer-options-at-a-fixed-1231-mhzFri, 11 Sep 2026 22:09:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:03071765-4eb6-4966-9949-9e5297c360faAriel NoprePart Number: LMX2571 Other Parts Discussed in Thread: LMX2572LP We are evaluating the LMX2571 as a fixed-frequency local oscillator for an L-band receiver, the payload of a 1P PocketQube. Supply current is our binding constraint. We are currently baselined on an ADF4351 at about 118 mA and are looking for something lower. Our configuration is a single output at 1231 MHz, never retuned: VCO 4924 MHz with CHDIV1 = 4 and CHDIV2 = 1, inside the 4300 to 5376 MHz range, integer-N. From Figure 61 we read about +1 dBm at 1200 MHz at the maximum power-control setting, push-pull, with the current curve reaching about 56 mA. Adding the 2.8 dB that Table 38 shows for the open-drain buffer with an LC pull-up suggests roughly +3.8 dBm at our frequency. Our mixer is a Mini-Circuits ADE-11X+, a Level 7 diode mixer needing +7 dBm, so we appear to be about 3 dB short. Three questions follow from that. 1. Supply current. Figure 61 plots current at 480 MHz only. What is the total ICC at 1231 MHz at the maximum output power setting, open drain? We expect it to be at or above the 56 mA shown for 480 MHz, and we need a figure we can put in a power budget rather than an extrapolation. 2. Combining the two outputs. Can RFoutTx and RFoutRx be enabled together as a fanout pair and summed externally to gain output power, or does the phase relationship between the ports make that impractical? If it is practical, what would the current penalty be? This matters because it would avoid a buffer stage entirely. 3. Buffer recommendation. If a buffer is unavoidable, which part would you suggest for about 4 dB of gain at 1231 MHz from a 3.3 V rail at the lowest possible current? We would also welcome a view on whether the LMX2572LP or another device in the family would be a better fit at 1231 MHz, since that frequency sits at the top of the LMX2571 range where output power is weakest. One piece of context on why the LO matters more than usual here: the receiver measures radio-frequency interference in the 1400 to 1427 MHz passive band, so LO spurs and phase noise translate directly into false detections. We would rather run the part at a setting we can justify than at its limit. Thank you. Engr. Ariel J. Nopre Jr. Project Manager and RF Lead, Team MASID IEEE GRSS 6th Student Grand Challenge University of the Philippines DilimanLMX2571LMX2572LPWearables (non-medical)https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1677956/lmk05318bevm-hardware-changes-for-programming-eval-through-external-controller/6481502Fri, 11 Sep 2026 21:12:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e55214d4-2764-415f-ad70-2ae1932eb3e7Connor LewisHi Akshay, Thanks for the clarification, I think I understand the issue now. That is odd that you're seeing more spurious behavior after the rework. I looked through your .tcs configuration and I don't see any obvious settings in the configuration which could introduce spurs. If one of the SMA ports was damaged that could affect the signal integrity of the output, but it's hard to say without seeing the EVM. Are you measuring the output single-ended, or differentially using a balun? Do you also have the correct termination for the AC-LVDS output format? And just to double check that the device is booting up correctly, can you try this startup sequence: 1. Power up LMK05318B or toggle PDN pin to trigger power-on-reset sequence 2. Read back all registers in TICS Pro 3. Load your .tcs file 4. In TICS Pro toolbar, click "Write all registers" 5. In TICS Pro toolbar, click "Soft-reset chip"https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1660960/lmk05028-2-loop-tcxo-dpll-mode/6481488Fri, 11 Sep 2026 20:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:230b2506-7dc5-4bf9-83eb-f07284102181Connor LewisHi Takumi-san, Sorry for the confusion, when I said "without using the TCXO input" I meant to check the 107MHz clock ppm error when the TCXO input is disconnected.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1677428/lmk05318b-unexpected-1pps-phase-offset-between-priref-and-out7/6481473Fri, 11 Sep 2026 20:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:774a4875-8c89-4695-8c3b-e6b87515ae45Connor LewisHi Serizawa, That's correct, R148 is stored in the internal EEPROM and is cleared by a power-on-reset. LMK5C33216A and LMK5B33216 are essentially the same device, the only difference is the BAW VCO frequency (2457.6MHz for LMK5CA, 2500MHz for LMK5B). Since the 50MHz and 10MHz output clocks can be easily divided from the 2500MHz VCO, I would recommend using LMK5B33216.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1677428/lmk05318b-unexpected-1pps-phase-offset-between-priref-and-out7/6481380Fri, 11 Sep 2026 18:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e6f56d60-663a-4923-9a0d-8f8e08d4a2e2Octo HalsemaBoth devices share the same architecture and physical pinout and the difference lies in the frequency of the BAW oscillator. LMK5C33216A optimized for 491.52 MHz multiples. LMK5B33216 Optimized for 312.5 MHz / 625 MHz multiples. Snippet from Figure 8-1. (both datasheets) Top-Level Block Diagram For 50 MHz, 10 MHz, and 1 PPS output I think the LMK5B33216 will be the best match. Please correct me if I'm wrong Connor/Jennifer? Your required frequencies can all be derived from DPLL3/APLL3 and phase aligned to the 1PPS reference. For best performance we also have to consider the XO frequency to be non-integer related to the output frequencies to minimize spurious noise. XO = 24.576MHz for example.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1681369/lmk03001-handling-of-unused-pins/6481344Fri, 11 Sep 2026 18:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:123d0f92-ed89-4b90-bbb1-54bf28c47816Michael SrinivasanHello, Yes, you are correct to leave these open. Thanks, Michaelhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1681586/sm320vc33-ep-v62-03610-01xe-external-clockFri, 11 Sep 2026 14:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4137c3ab-6be6-4163-b5f9-11879cf0f651Long NguyenPart Number: SM320VC33-EP Hi, Could you please support me on this specific TI PN "V62/03610-01XE"? The datasheet on Page 32, "Timing Requirement for EXTCLK", show the Rise/Fall Time Max is 4ns. If I have Oscillator with Rise/Fall Time of 10ns, would it still work? What is the lowest allowable for Rise/Fall Time on EXTCLK pin? What is the recommend ppm for Oscillator? Thank you very much.Aerospace & DefenseSM320VC33-EPhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1681543/lmkdb1112-purchase-of-lmkdb1116-and-its-lead-timeFri, 11 Sep 2026 11:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9f762fa4-b795-4f85-8d22-e2019eafa245Vasavi RevadiPart Number: LMKDB1112 Other Parts Discussed in Thread: LMKDB1116 We are looking for replacement to MPN RC19016A100 from Renesas, TI suggests LMKDB1116 as drop in replacement. But we are not able to find details on purchase and design from website. Can you please let us know is it it market? whats the lead time? also share documents apart from datasheet.LMKDB1112LMKDB1116https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1681463/cdce62002-alternative-recommendation-for-cdce62002Fri, 11 Sep 2026 08:49:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9a8f55a9-4390-4539-a6eb-4d90b259a159KyoheiPart Number: CDCE62002 Other Parts Discussed in Thread: CDCM6208 , LMK03328 , CDCM6208V1 , CLOCKPRO Hi team, My customer is evaluating potential replacement devices for CDCE62002 and would appreciate your guidance on suitable alternatives within the TI clock portfolio. The current design uses CDCE62002 as a programmable PLL clock generator. Typical output frequencies include 148.5 MHz and 297 MHz, and the device is configured dynamically through FPGA register programming. We have reviewed several TI clock generator families and are currently considering: CDCM6208 LMK03328 While reviewing the datasheets, we noticed the following VCO frequency ranges: CDCM6208 CDCM6208V1: 2.39 GHz to 2.55 GHz CDCM6208V2: 2.94 GHz to 3.13 GHz LMK03328 VCO frequency range: 4.8 GHz to 5.4 GHz We would like to understand: Are CDCM6208 and/or LMK03328 recommended replacements for CDCE62002? Is there another TI device that would be considered a closer functional replacement? When evaluating migration from CDCE62002, what are the key architectural differences that should be reviewed? PLL architecture Divider limitations VCO operating range Register configuration and programmability Output format support For designs requiring output frequencies such as 148.5 MHz and 297 MHz: Are there any limitations or considerations when generating these frequencies using CDCM6208 or LMK03328? Can TI provide ClockPro configuration examples that generate 148.5 MHz and 297 MHz outputs using CDCM6208V2 and/or LMK03328? Are there any recommended VCO and divider settings for these output frequencies? Is there any recommended migration path, application note, or reference design available for customers moving from CDCE62002 to newer clock generator families? Any guidance would be greatly appreciated. Thank you. Best regards, KyoheiLMK03328CDCM6208V1ClockProCDCM6208CDCE62002https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1676765/lmx2820-external-pfd-topology-of-lmx2820/6480529Fri, 11 Sep 2026 06:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a527a4c7-da70-4a82-b855-052ea0382b11xiandao langCould someone kindly answer this?https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1677956/lmk05318bevm-hardware-changes-for-programming-eval-through-external-controller/6480470Fri, 11 Sep 2026 05:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e2d5d5af-a744-4918-82b8-39ab5e831a8dAkshay RathodWe are using the LMK05318BEVM in our up-converter to give reference for the LMX2595. We made the hardware modifications as discussed in the TI E2E thread to enable programming through an external controller. After the modification, we observed additional spikes in the system-level phase-noise measurement . The phase-noise performance of the LMK05318B is also attached for reference, which shows some spurious, however, the integrated system phase-noise plot shows discrete spurious components that were not present in our previous measurements. Furthermore, after reverting the hardware modifications and restoring the original EVM configuration, the system-level phase-noise performance has not returned to the previous baseline, and the additional spurious components are still observed. Could this be related to a grounding issue, since after I put the top plate of the enclosure, one of the spike reduced. Now the PCB is standing on studs; we are planning to make a ground plate for it to rest. Your guidance would be helpful. Also attached is the .tcs file for reference. e2e.ti.com/.../UP_5F00_MANUAL-HOLDOVER.TCShttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1681369/lmk03001-handling-of-unused-pinsFri, 11 Sep 2026 05:19:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:43b37f99-a164-47aa-bd56-5a535d6de313user6004480Part Number: LMK03001 Hi expert, We want to confirm about the handling of unused pins. We are not using the following pins and are handling them as described below. Is it correct to assume there are no particular issues? Fout: open CLKout0-3,5-7: open CLKout0-3,5-7*: open *Output is disabled via register settings for all pins.LMK03001Medical & healthcarehttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1679938/tms320f28p559sg-q1-is-a-software-reset-triggered-by-writing-a-value-other-than-101-to-the-wdchk-bits-effective-even-when-intosc1-is-stopped/6480398Fri, 11 Sep 2026 03:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8fa1cbee-8302-42ee-83f3-fbfb8cf4e627user6240569Thank you for the prompt reply. Regarding the soft reset method, I will consider alternatives other than using the WDCHK bits.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1679938/tms320f28p559sg-q1-is-a-software-reset-triggered-by-writing-a-value-other-than-101-to-the-wdchk-bits-effective-even-when-intosc1-is-stopped/6480395Fri, 11 Sep 2026 03:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1996429d-459a-42e8-a61d-64bfb08b9ef7Vivek SinghIf INTOSC1 is stopped or damaged then WD may not be able to reset the device. To avoid this, user need to use DCC to monitor these clocks. Vivek Singhhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1679938/tms320f28p559sg-q1-is-a-software-reset-triggered-by-writing-a-value-other-than-101-to-the-wdchk-bits-effective-even-when-intosc1-is-stopped/6480390Fri, 11 Sep 2026 03:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:59173d2b-bf65-40d2-8971-883938c1fb58user6240569The message shown above appears, and past E2E information cannot be viewed. Could you please provide the correct, accessible URL?https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1679938/tms320f28p559sg-q1-is-a-software-reset-triggered-by-writing-a-value-other-than-101-to-the-wdchk-bits-effective-even-when-intosc1-is-stopped/6480364Fri, 11 Sep 2026 03:12:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:42531e41-2125-414c-bf57-e6198c520859Vivek SinghPlease refer this E2E post - https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000-microcontrollers---internal/f/c2000-microcontrollers---internal-forum/1669255/tms320f28p559sj-q1-wdt-how-to-issue-reset-if-intosc1-stops-accidentally Regards, Vivek Singh