https://e2e.ti.com/support/clock-timing-group/clock-and-timing/ Products covered in this section are Clock Generation & Distribution, Memory Interface, Registers, Real Time Clocks and Timers. en-USTelligent Community 13https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1660787/cdclvp111-sp-test/6404604Fri, 03 Jul 2026 14:12:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:593b184e-c3db-44dc-a484-11f9fc80ea1fMark CaskeyThe objective is to calibrate out the variations in propagation delay over temperature and time (any aging effects and radiation effects). The system tracks temperature and time. Do you have any test data on this, or advice on if that is feasible? As we can track temperature and time, and would test on each part (compensating for process variations). How much variability form other factors would there be left? We cannot track variation in the power rails. Will a small variation of the power (still in spec) be a significant contributor? We can irradiate devices to reflect increasing radiation exposure. Will that be a significant contributor? IE is it worth doing?https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1655066/lmk3h0102-part-with-1-2v-io-vcc/6404590Fri, 03 Jul 2026 14:08:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e360108d-d9b0-4212-b880-ce85f7fad4e6Mansoor AhmedHi Sandra, OK, sure, so the results shared by Jaryd for our reference frequencies were generated by internal clock source of the LMK3H2108 device. I though with internal source the jitter spec is much lesser as shown in JITTER CHARACTERISTICS page 13 & 14. can you please confirm? If I use external clock source as reference and use LMK3H2108 as buffer, will the jitter be same as above or more?https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1661093/tps3813k33-ep-tps3813k33qdbvrq1-statistical-dataFri, 03 Jul 2026 12:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:27ca85f1-7772-43ce-b86b-2ebedf099cbfMarco KnausPart Number: TPS3813K33-EP Hello We are using the window watchdog mentioned in the title to verify proper operation of our CPU. We have observed a higher number of devices on the lower end of the tolerance band in the recent past. Could TI support our investigations with statistics acquired during the production of this chip? Has there been a silicon revision in the last couple of months or years? Regards, Marco KnausTPS3813K33-EPhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1659781/lmk1d1204-how-to-couple-lmk1d1204-to-clipped-sine-vcxo/6404294Fri, 03 Jul 2026 08:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1c7af40f-50c3-4964-8cd7-73414965a155Miguel SThanks Michaelhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1660960/lmk05028-2-loop-tcxo-dpll-modeFri, 03 Jul 2026 07:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a9246b24-2f9d-40c1-8b22-4b3e539916ddTakumi Suzuki1Part Number: LMK05028 Hi, I would like to ask for your assistance with 2 points about clock generation using the LMK05028 as below. Q1) In 2-Loop TCXO-DPLL mode, when generating a clock, I understand that the output clock ahould be dependent on the TCXO's frequency deviation. However, even when LOS_TXCO and LOS_FDET_TCXO are not occurring, the output clock is dependent on the XO's frequency deviation. * This appears to be operating as if the TXCO-DPLL is unlocked and the clock is being generated only by the APLL. The detected alarms are : - LOPL_DPLLx - LOFL_DPLLx - HLDOVRx I understand that all of these represent alarm states for the REF-DPLL. Are ther any settings I should be aware of? Q2) Also, the register types for LOS_TXCO and LOS_FDET_TCXO are read. When an alarm is detected, does the detection state persist until a read access occurs? * If it was not a latch hold, does that mean that the TCXO alarm was not detected at the time of the read access? Is that correct? Many thanks for your strong support. Best Regards, TakumiWired networkingLMK05028https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1659562/lp5815drlevm-about-internal-oscillator-frequency/6404047Fri, 03 Jul 2026 05:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6f50f4f2-f2b2-42b8-a0fc-ec2da97eddd4yuko yamazakiUnderstood. Thank you very much.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1659562/lp5815drlevm-about-internal-oscillator-frequency/6404042Fri, 03 Jul 2026 05:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c3146da4-d865-4a49-8a29-8a5e399c6495Hongjia-WuHi Yuko, Sure. We have got your email and we will provide an update soon. I will close the thread here first. Regards, Emma Wuhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1659574/lmx2572lpevm-phase-noise-in-vco3/6403921Fri, 03 Jul 2026 02:51:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f3757a48-d114-46f2-b2ef-82f7ed065f4dkeita matsuzakihttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1659574/lmx2572lpevm-phase-noise-in-vco3/6403918Fri, 03 Jul 2026 02:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ab1e0306-dd0b-44bc-bffa-45712b9a5fbekeita matsuzakiThank you for your reply. I apologize for the insufficient explanation. I have attached the TICS Pro settings screen as Figure 1. Your VCO frequency is 4528.4MHz, according to the datasheet, VCO4 should not be able to support this frequency. ⇒That is correct; however, in practice, the VCO bank during calibrateVCO changed significantly when we executed the calibration using the VCO Assist settings. 　There was also some variation depending on temperature (on the order of a few 100kHz at RFout). 　 In fact, it locked to VCO4 at a frequency of 4528.4 MHz, and the measured phase noise was close to the simulation results. 　 Therefore, we understood the VCO frequency range values in the datasheet as being for reference only. 　In addition, what we are currently concerned about is the phase noise of VCO3. (These are the supported frequencies for VCO3.) 　The phase noise of VCO4 was attached for comparison purposes. 283.025MHz R110(rb_VCO_SEL) : 3 R111(rb_VCO_CAPCTRL) : 182 R112(rb_VCO_DACISET) : 7 283.05MHz R110(rb_VCO_SEL) : 4 R111(rb_VCO_CAPCTRL) : 69 R112(rb_VCO_DACISET) : 0 The phase noise bump seems to be due to spurs randomization from PLL_DEN, MASH_ORDER and PFD_DLY_SEL. ⇒The settings for PLL_DEN, MASH_ORDER, and PFD_DLY_SEL are as shown in the attached image. I tried changing the values of MASH_ORDER and PFD_DLY_SEL to various settings, but the phase noise did not improve. My question is about the MASH_ORDER setting: when using integer mode, does it have any meaning to set the Order Modulator? Also, what is spur randomization? 283.025MHz PLL_DEN : 11321 MASH_ORDER : Integer Mode PFD_DLY_SEL : 1 283.05MHz PLL_DEN : 11322 MASH_ORDER : Integer Mode PFD_DLY_SEL : 1https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1657443/lmx2492evm-active-loop-filter-troubleshooting/6403834Fri, 03 Jul 2026 00:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:40011dc1-76e3-42c2-b888-59e6e4bccca7Noel FungHi Domenico, Here is my configuration. e2e.ti.com/.../2492-active-filter.txt e2e.ti.com/.../2492-active-filter.tcs Operation current is 240mA, including the onboard XO. Power down current is 190mA.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1660638/lmx2572lp-lmx2572-occasional-missing-ld-rising-edge-during-hopping/6403813Fri, 03 Jul 2026 00:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:db6cbfd8-9e9a-436b-98aa-fa3c905090e7Noel FungHi There, To debug, suggest use a scope to monitor the waveform on the Vtune pin to confirm the lock status.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1659267/lmx2572-sync-and-mash_seed-function/6403809Fri, 03 Jul 2026 00:08:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:090c8b90-7943-48f6-a9e0-56ce16977c3bNoel FungHi There, The channel divider and IncludedDivide are different in LMX2572, that monotonic characteristic in LMX2594 does not happen on LMX2572, at least, we haven't found a configuration can replicate this problem so far.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1659574/lmx2572lpevm-phase-noise-in-vco3/6403801Thu, 02 Jul 2026 23:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:faa4ad51-0904-4ccb-9ced-145b4ead0120Noel FungHi There, Your VCO frequency is 4528.4MHz, according to the datasheet, VCO4 should not be able to support this frequency. Are you sure the PLL is able to lock with VCO4? Can you do a register read back to R110, R111 and R112 to confirm? The phase noise bump seems to be due to spurs randomization from PLL_DEN, MASH_ORDER and PFD_DLY_SEL. Could you share your register configuration, preferably in TICS Pro format? For example,https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1660437/tlc555-rma-2026-09113/6403785Thu, 02 Jul 2026 23:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:62221c3e-9de1-46fa-9e9e-1dd1eed8c5a6Ron MichallickRuby, OA is 0A ; probably 2020 October; but 2010 October or earlier is possible. 3C is probably 2023 December; but 2013 December or earlier is possible. The last three characters are encrypted. The markings affect a vast number of TI part as part of a symbolization PCN in 2021.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1660816/cdclvp111-sp-cdclvp111-clk_sel-pulldown-resistor-needed/6403782Thu, 02 Jul 2026 23:19:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2d4cb070-a02e-4923-9b8e-0d57930c5606Michael SrinivasanHi Will, A 1kOhm resistor would be an appropriate value. Thanks, Michaelhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1660787/cdclvp111-sp-test/6403778Thu, 02 Jul 2026 23:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9f5b1657-a78e-4d31-87aa-4036d5a70a1dMichael SrinivasanHi Mark, I'm going to have to run this question by our packaging team. I provided a tpd shift per degree Celsius in the above E2E, and I would think that would apply under the same circumstances of radiation - radiation would in theory increase the operating junction temperature of the device. My understanding of the physical material of the device is limited, so let me ask our experts. I will get back to you next week. Thanks, Michaelhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1660655/cdclvc1103-clock-buffer-for-10pf-load/6403771Thu, 02 Jul 2026 23:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:29e60599-a045-478e-886c-31bc5e8673d6Michael SrinivasanHiromu-san, The LMK00105 was tested with 10pF capacitive loads, but I the LMK1C110x would have a sufficiently high drive strength to operate in this scenario - the LMK00105 may be a bit of overkill for a standard LVCMOS buffer in this scenario. Thanks, Michaelhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1659619/lmk04828-ep-review-and-suggest-correction-for-hardware-design/6403752Thu, 02 Jul 2026 22:44:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:248ef565-c1e6-48d9-be17-aa445d77ce1bMichael SrinivasanHi Gaurav, Unfortunately, that output combination is not possible, as the LCM of these two numbers is not within the output range that can be achieved by the internal VCO. Thanks, Michaelhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1660787/cdclvp111-sp-test/6403557Thu, 02 Jul 2026 19:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:24f33d48-5b51-400a-8c9f-bb35b0d6b409Mark CaskeyHi Michael is there any anticipated increase of the propagation as radiation exposure increases?https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1660327/cdcvf25081-feedback-input-non-monotonicity/6403531Thu, 02 Jul 2026 19:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:670ad685-c445-4dca-a462-b6ed4490b124Jennifer HHi Michael, By unused, I mean unloaded. The datasheet specifies tying the FB pin to one of the clock buffers' outputs to complete the feedback loop of the internal PLL. When I said unused, I meant one of the clock buffer's output pins that is only tied to feedback and not connected to another receiver as well.