https://e2e.ti.com/support/clock-timing-group/clock-and-timing/ Products covered in this section are Clock Generation & Distribution, Memory Interface, Registers, Real Time Clocks and Timers. en-USTelligent Community 13https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1644644/cdc6c-2-4ghz-emissions-causing-wi-fi-bt-desense/6345707Thu, 14 May 2026 16:39:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bee657c9-3c0a-4cfb-950d-e82c70d63bf8Connor LewisThanks for the update here, hopefully the layout optimizations will solve this issue on the next build. I'll go ahead and mark this thread as resolved but feel free to create a new thread if you have any other questions.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1642907/lmk05318bevm-spikes-observed-in-the-phase-noise-of-100-mhz-output-from-lmk05318b-eval-board/6345695Thu, 14 May 2026 16:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:77a05ca0-2288-4527-bd0c-17e4095b7f24Connor LewisHi Suchitra, You can disregard the error message in TICS Pro, the .tcs file should still be functional even if those registers are not imported. Does the updated profile I sent have different performance on your setup compared to the previous config? If SECREF is considered valid even when no input is being applied, you may need to enable reference validation on SECREF. I would recommend enabling the frequency detector, this should guarantee that SECREF will not be considered valid if no input is present. For more information on the lock acquisition logic you can refer to Figure 8-16 from the device datasheet: Essentially if manual holdover is selected, the DPLL will only be allowed to lock to the selected input. If auto non-revertive is chosen, then the DPLL will try to lock to the highest priority valid reference instead of entering holdover.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1645060/tlc555-component-value-setting/6345686Thu, 14 May 2026 16:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ea0e66fc-110d-4298-8ecf-64f7cda0b3f5Ron MichallickEileen, [Ra, Rb, Rd] = [10k, 169k, 243] = 403Hz, 50.0% typicalhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1644644/cdc6c-2-4ghz-emissions-causing-wi-fi-bt-desense/6345680Thu, 14 May 2026 16:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:590f7451-5f28-4bf4-9b3b-891c3e8172a2Adam LockHello Connor, Yes we did see an improvement. We saw a 24.09dB improvement at CH1 (2412 MHz) and 34.24dB improvement at CH13 (2472 MHz). I am going to leave the oscillator footprint on the PCBA for the next build, but change to the DLX package (DLY out of stock), add a capacitor bank targeting 2-3GHz, and a ferrite bead isolating the oscillator from the power net. I have found a few Murata ferrites that specifically work in the 2.4GHz band where SRF is not an issue.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1644644/cdc6c-2-4ghz-emissions-causing-wi-fi-bt-desense/6345619Thu, 14 May 2026 15:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f102cf24-f59f-4dc2-84a8-e25edfd72f0cConnor LewisHi Adam, Regarding the layout differences between the CISPR test board and the EVM, we didn't necessarily make these changes to target specific emissions. The intention was to minimize the output trace length and reduce the impact of the output trace in the EMI results. For this compliance testing we typically just want to validate the intrinsic noise of the oscillator. The bypass caps were optimized to reduce the oscillator switching noise from feeding back into the power supply and radiating throughout the power plane. I believe we chose caps which had very low impedance at the switching frequency (25MHz), as well as the equivalent frequency of the rise time (1 / 1.47ns = 680MHZ for slow mode 2 variants). Did you see any improvement after testing with the xtal?https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1641543/lmk04821-pll-with-low-noise-and-jitter-cleaner/6345605Thu, 14 May 2026 15:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4bbebc95-dd71-4cc9-9c35-2120fc442297Noel FungHi Yoav, Differential signal transmission is usually point to point, a fanout buffer is required to make multiple copies.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1645060/tlc555-component-value-setting/6345597Thu, 14 May 2026 15:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a7b45119-f8d6-4f51-85f8-7b40c2d3c17aEileen HuHi Ron, Thank you for your reply. I'd like to confirm that, for 400Hz output, can we keep the RA=10K, but change RB to 174K? Regards, Eileenhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1645983/lmx2594-the-device-locks-and-after-some-time-unlocksThu, 14 May 2026 15:16:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2e7c60b7-3ecf-4a5d-9778-d5e6f829b3d3Gabriel SantosPart Number: LMX2594 Hello. I have a design with the LMX2594 that should be locking at 7.26GHz. I have tested the design in more than one board and I have experienced after some time working under harsh conditions, the output frequency to shift from the desired frequency to a frequency ~100MHz to the left, and keeps drifting around it. This seems to me, related to temperature rise. Recently, this is happening ~30s-1m after turning on, in situations that it would never happen. I have tested to improve the margin phase of the loop filter from 48º to 65º, as it could be the filter to be unstable, but without success. I am using the following configuration.LMX2594Wireless Infrastructurehttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1641543/lmk04821-pll-with-low-noise-and-jitter-cleaner/6345285Thu, 14 May 2026 11:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:befc0a4b-a430-42ab-b75f-277f81cfd449Yoav BenitaHi Noel, sorry for the delay. Does the LMK04821 support using one SYSREF (One Shot) output for all my 8 slaves(Fanout 1->9) (capacitance, driving capability etc.)?https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1645750/cdce6214-design-reviewThu, 14 May 2026 06:43:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8d925cbd-f9de-432a-92e5-9160a85f5d81JH ShinPart Number: CDCE6214 Hello, My customer requests a design review for CDCE6214RGER. Please review the design of the file below to see if there are any issues. CDCE6214RGER_260514.zip Thank you.CDCE6214https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1642907/lmk05318bevm-spikes-observed-in-the-phase-noise-of-100-mhz-output-from-lmk05318b-eval-board/6344906Thu, 14 May 2026 06:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0d500e6a-6c57-4764-aac1-e5761ac742b9Suchitra RamamoorthyHi Connor, I tried to load the tics file you gave me. But after loading it shows this:- "Loaded TCS file. These registers were present in the loaded TCS file but not in current profile:R148, R169." Also can u please tell me how I can check whether DPLL is locking in both modes and how I can verify same performance. What I thought was to verify same functionality I should try to validate whether my outputs are synced with the external PRIREF when it is present and in holdover mode when the reference is not connected. But I don't know how to do that. What I already observed was in the auto non revertive mode, when I remove the reference the status is not exhibited as holdover on the gui it instead shows reference as SECREF even though it's not connected. Whereas in the Manual Holdover mode, when PRIREF is present it shows status as PRIREF and when reference is disconnected it shows Holdover. I couldn't not understand why both modes show different behaviour. Actually we wanted to have a receipt of whether the lmk is locked to the active reference or in holdover mode which is why we shifted to manual holdover mode from auto non revertive mode.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1645537/cdce6214-clock-problem/6344807Thu, 14 May 2026 04:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3eccf561-9a61-4d09-8661-a4a4befe1aa9Ken LiHi Jaryd, Thank you for your reply. I'm the customer in the original question. So from your message that the CDCE6214 will output 128/7MHz frequency according to the configured parameters. So my further question is that how to can get the right CDCE6214 loop filter parameters for my design. It looks like that the loop filter data never change according to any frequency whatever I set... (the loop filter data showing on tics pro never change) Is there any solution to this? Thank you and I'm looking forward to hearing from you. Best, Kenhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1644786/cdce925-cdce925-can-generate-the-freq-not-from-i2c/6344698Thu, 14 May 2026 03:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3147e18d-0e5d-427c-83a2-ee64277302c2Sean Liao (Yu-Sheng)Hi Jryad, Hope to receive your question soon, thanks a lot!https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1645537/cdce6214-clock-problem/6344577Thu, 14 May 2026 01:09:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5e498be9-2542-47fd-bafe-952623f53b65Jaryd DukesHi Danilo, I was able to replicate this error on my end as well, it looks like this is a bug with how TICS Pro calculates the frequency plan given an output that has infinite decimal places. If you mouse over the frequency, it will display a tooltip that tells you the exact frequency as a fraction (see below). This should only affect this specific feature of TICS Pro, and the CDCE6214 should be able to output this frequency just fine with these settings. Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1645331/cdce6214-cdce6124-syntonized-clock-servo/6344546Thu, 14 May 2026 00:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:58dbcb49-5185-4668-98c2-3c32bdd9538fJaryd DukesHi Tobias, We're currently looking into your query, we will get back to you within the next few days. Best, Jarydhttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1643795/lmk00105-availability-for-data-transmission/6344534Thu, 14 May 2026 00:10:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:77754b63-1257-47ce-af2b-f6b5e7dfa7ecTakashi ImaiHello Michael-san, Thank you for your reply. I would reply to customer that LMK00105 is ok for thier application. Thank you, T.imaihttps://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1645060/tlc555-component-value-setting/6344354Wed, 13 May 2026 21:08:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:10b60689-bec3-4fad-ac6c-fdcad0afc56bRon MichallickEileen, The full FAQ is here: [FAQ] How do I design a-stable timer, oscillator, circuits using LMC555, TLC555, LM555, NA555, NE555, SA555, or SE555? Frequency is inverse to resistors. They could factor the resistors by 500/400 = 1.25 the previous value RA 12.5k (12.4k) , Rb = 166.25k (165k), Rd = 376 (374 ohms)https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1645060/tlc555-component-value-setting/6344089Wed, 13 May 2026 17:43:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:28acc122-78a5-4685-84b5-28e62a9b29b6Ron MichallickEileen, I have no requirements for precision. The main point of the table was to convey the point that output is about 500Hz and 50% 1% resistors are fine. RB being 0.1% in table is point out that it is the most important resistor (of the three). The 5% for cap is to point that the capacitor is the main cause of output variance. It's tolerance, voltage and temperature modulations.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1644742/lmx2595evm-usb2any-firmware-update-failure/6344064Wed, 13 May 2026 17:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1d5131db-58c8-4584-999b-046d06b88294Noel FungHi There, 2.7.0.0 is more than a decade old, it is not supported by TICS Pro. Could you try below? 1. Download USB2ANY Firmware Loader ( https://dr-download.ti.com/software-development/firmware/MD-063xo7KvuK/01.00.00.00/snvc166.zip ), unzip the .exe file to a folder. 2. Copy USB2ANY.dll from C:\Program Files (x86)\Texas Instruments\TICS Pro to the same folder of firmware loader. For example: 3. Save below text file to c:\Program Files (x86)\TI USB2ANY SDK\Firmware. e2e.ti.com/.../6560.USB2ANY_5F00_2_5F00_9_5F00_1_5F00_2.txt 4. Connect Reference Pro board to the PC via USB cable 5. Run USB2ANY Firmware Loader.exe 6. Click Yes 7. Click Cancel 8. Click Update Firmware . Make sure the correct text file is shown in "Update to firmware" pull down menu. 9. Click Yes 10. Follow the onscreen instruction to complete the update. I hope this works.https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1645060/tlc555-component-value-setting/6343737Wed, 13 May 2026 14:43:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:add7ac28-e62c-48fb-8415-99847605ad2cEileen HuHi Ron, What the precision requirements for the components? Are they listed in the first column of the table? If so, 0.1% tolerance resistors are not available in the customer's component library. Can they replace RB with 1% tolerance one? Regards, Eileen