• Apr 4, 2013

    New Video Series for CDCE(L)9xx online

    <p>New Video Series for CDCE(L)9xx in 3 parts explains the EVM Hardware, Software and Feature Set.</p> <p>The Videos can be watched below or you visit on of the products homepage with further information about EVMs and Software&nbsp;(e.g: <a href="http://www.ti.com/product/ cdce949 #videoheader">http://www.ti.com/product/ cdce949 #videoheader</a>).</p> <p><...
    • Mar 7, 2013

    CDCE62005: Advanced GUI Available (w/ ini file sanity checker)

    The newest CDCE62005 GUI got improved to work under WinXP/Win7 32bit/64bit. In addition it includes a sanity check for ini files. By loading an ini file into the GUI the sanity checker starts and highlight wrong bit settings. Gui available at: http://www.ti.com/litv/zip/scac105e
    • May 30, 2012

    CDCM6208 GUI video 1 online

    The CDCM6208 clock synthesizer was released to mass production today. http://www.ti.com/product/cdcm6208 To assist with using the GUI , the following video is available: http://www.youtube.com/watch?v=RUhTM7XtA-E
    • Apr 26, 2012

    CDCM1802/CDCM1804: enabling, if input clock is applied

    In the datasheet TI describes that the device needs 1us to settle internal voltages and bandgap after EN goes high: However, if the input clock is already available, there is no issue to enable the outputs of CDCM1802 / CDCM1804 . The device still need 1us to have a stable output clock with full swing: To avoid undefined pulses during the 1us settling time, it is allowed to do a power sequencing. The CDCM1802...
    • Feb 24, 2012

    CDCE72010 input termination schemes explained (2)

    Here is a link to a nice presentation of different input termination schemes for the CDCE72010 : http://e2e.ti.com/support/clocks/m/videos__files/610618/download.aspx
    • Jan 17, 2012

    CDCM6100x frequency planner - simple Excel tool available on E2E

    Here a great little tool helping to quickly configure the CDCM61001 , CDCM6102, or CDCM61004 . http://e2e.ti.com/support/clocks/m/videos__files/576535.aspx
    • Dec 14, 2011

    The LVDS clock Buffer families CDCLVD12xx and CDCLVD21xx offer failsafe inputs

    We can confirm that the 2.5V LVDS clock buffer family offers failsafe inputs. This means the clock input signal can already be applied to the clock buffer while power is still ramping. We will in the near future adjust the absolute max ratings in the data sheets accordingly to reflect this. While the website of the device already mentioned failsafe in the past, the data sheets in the absolute maximum section still...
    • Apr 17, 2011


    The Hardware Design Guide for KeyStone Devices found at http://www.ti.com/litv/pdf/sprabi2 refers to the CDCM6208 , which is not yet released on the TI external web. If you have any question in regards to the CDCM6208 , please send an email to the following email address, and a TI sales representative will respond to you shortly: cdcm6208_inquiry@list.ti.com Much thanks & Best regards, Fritz update 01...
    • Oct 21, 2010

    Clocking ADC and DAC - useful application notes

    I just happened to train distribution FAEs and found a general interest into the topic of clocking ADCs and DACs. Maybe there is a wider need out there? Here my 3 most favorite application notes on this topic: ADC clocking in general (great and comprehensive) : http://focus.ti.com/lit/an/slyt075/slyt075.pdf addl ADC clocking - determining the integration range: http://focus.ti.com/lit/an/slyt379/slyt379.pdf...
    • Oct 21, 2010

    CDCE62005 GUI - now offers reverse frequency planning AND we overhauled the loop filter tool completely!!!

    update 10/20/2010: We just overhauled the CDCE62005 GUI integrated loop filter tool. We departed from the Excel sheet approach, and ported a graphical loop filter interface instead into the GUI. You can now get the right R & C recommendations based on your desired loop filter bandwidth, phase margin, and jitter peaking. To try out the new tool, go here: http://e2e.ti.com/support/clocks/m/videos__files/224554.aspx...
    • Oct 20, 2010

    Clocking High-Speed Serializer and De-Serializer - New article published at Planet Analog by John Johnson, Manager, Market Development and Systems Engineering, Texas Instruments

    Planet Analog just published an article about High-Speed SERDES clocking written by John Johnson. You can find the article at: http://www.eetimes.com/design/analog-design/4208825/SIGNAL-CHAIN-BASICS--46--Basics-of-clock-jitter-specifications-in-high-speed-links--Part-I-?cid=NL_PlanetAnalog&Ecosystem=analog-design Enjoy the reading! Fritz (TI Clocks & Timing Products)
    • Sep 1, 2010

    CDCE62002 and CDCE62005 SPI related upnote was updated and now posted on E2E

    A new revision of the CDCE6200x SPI interface is posted at: http://e2e.ti.com/support/clocks/m/videos__files/180965.aspx
    • Aug 19, 2010

    What if the CDCE62005 Excel Loop Filter Calculator causes me trouble?

    Did you know that the CDCE62005 comes with the ability to utilize an internal PLL loop filter or an external loop filter? When using the external loop filter on the CDCE62005 EVM, you actually can choose from 5 different external filter. BUT: What do you do if the bandwidth calculator embedded into the CDCE62005 always cause a runtime error? Here is the solution: Problem: CDCE62005 Loop bandwidth Excel file doesn't...
    • Aug 19, 2010

    TI Clocks - PLL Loopfilter tool

    TI PLL loop filter tool available here