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LMX2592EVM: Reducing the spurs for ~1G and 2G signals

Part Number: LMX2592EVM
Other Parts Discussed in Thread: LMX2592, PLLATINUMSIM-SW

LMX2592

  • I am using a LMX2592 as a synthesizer to generate approximately  1G and 2G signals using 10M Osc
  • I am observing some spurs at less than 10KHz offset  from the carrier signal
  • I have tried to reduce the Loop Filter Bandwidth as per datasheet recommendations( http://www.ti.com/lit/ds/symlink/lmx2592.pdf )
  • Referred to section 8.1.2 spur mitigation techniques
  • Can you please let me know other ways to reduce the spurs lower than 10 KHz offset ?

  • Hi Vikram,

    I would start trying to narrow down where the spurs came from. You can try:
    - using the 100MHz XO on the EVM and see if there is difference
    - try using a signal generator
    - another power supply

    Which offset exactly do those spurs occur?

    because if they are not right on 10kHz and its harmonics, it is possibly spurs generated somewhere from the setup.

    Regards,

    Brian Wang
  • Hi Brian ,

    When using the same source as Fref in (100MHz and 10MHz) we see spurs in 10MHz case

    if possible we would like to use a 10MHz XO.

    When using a 10Mhz XO, the spurs occur at ~3.5KHz offset , -48dBc/Hz amplitude. 

    Please let us know if there are ways to mitigate this spur.

    Regards,

    Vikram

  • Hi Brian,

                 Some more observations

    • Also it was observed that the spur frequency was changing when we changed the charge pump gain or gain multiplier.
    • The spur is coinciding with the edge of the loop bandwidth.
    • Can you please let me know how to mitigate this spur ?

    Regards

    Vikram 

     

  • Hi Vikram,

    Could you provide us a screen shot of TICS Pro configuration as well as the schematic of your loop filter?
  • Hi Noel,

    • Schematics of the Loop Filter ( C1_LF : 1nF, C2_LF 0.1uF,R2_LF : 75 ohms)

    Please find the  TICS Pro Configuration Settings Below:

    • Fosc: 10MHz
    • Doubler , Pre-R, Multiplier, Post-R settings x1
    • Charge Pump: 0.312mA, Gain Multiplier x1
    • Pre Scalar:  2 ,N divider 300 ,
    • Fnum : 14000, Fden: 66667
    • FVCO: 6004.199979 MHz
    • RF Out A : 2001.399 MHz
    • Power: 15
    • Please find the snap shot attached

  • Hi Vikram,

    According to your configuration and loop filter, the loop bandwidth is approx. 3.5kHz but phase margin is 9.26deg. So the output phase noise response should has a serious peaking at 3.5kHz.
    What is the phase noise or jitter specification you are looking for? We can help provide a suggestion on loop filter and configuration.
  • Hi Noel,

    • We are doing fine on the Phase noise measurements for offsets upto 20MHz (existing Charge pump settings gives us optimum phase noise)
    • We need to reduce the spurs to lower than 90 dBc (for offsets less than 20MHz)
    • We don't see these spurs when using a 100 MHz Fref
    • How can we mitigate the spur's for 10MHz Fref ?

    Regards,

    Vikram

  • Hi Vikram,

    When you use 100MHz ref, did you change the configuration? For example, what is the fpd in this case?
    If you simply change the ref from 10MHz to 100MHz, then fpd will become 100MHz. Now your loop bandwidth is 11.7kHz and phase margin is 28.6deg, peaking will not be too bad.
    Anyway, I suggest you redesign your loop filter to make the phase margin higher. This could (1) reduce the peaking and (2) make the loop more stable.
  • Hi Noel,

    • Can you please suggest Loop filter values ?
    • Currently used filter values ( C1_LF : 1nF, C2_LF 0.1uF,R2_LF : 75 ohms) CP Gain 0.312mA

    Regards,

    Vikram

  • Hi Noel,

    In addition to my earlier comment :

    R3_LF,R4_LF and C4_LF are default values

    Regards,
    Vikram
  • Hi Vikram,

    I know you want to use 10MHz reference clock. Is the output frequency 2001.4MHz? What is your phase noise requirement?
    Here is an example with a 5kHz loop bandwidth design.

    fpd = 10MHz; effective charge pump gain = 0.3125mA
    C1 = 1.8nF; C2 = 56nF; C3 = 5.6nF; R2 = 1.5k; R3 = 0.47k
  • Hi Noel,

    • Yes, the output frequency is 2001.4 MHz ,
    • Thanks for your Loop band width setting values
    • Our phase noise requirement at different offsets: 300Khz :  (-132 dBc/Hz) , 400KHz : (-132 dBc/Hz) , 600KHz : (-133.3 dBc/Hz) , 800KHz : (-134.9 dBc/Hz) , 1.6MHz : (-142.2 dBc/Hz) , 3 MHz : (-150.5 dBc/Hz) ,6 MHz : (-155.7 dBc/Hz) ,10 MHz : (-157.9 dBc/Hz) , 20 MHz : (-157.9 dBc/Hz)
    • Can you please let us know how to compute the Loop filter bandwidth and component values ?
    • Can you please let us know how to compute the phase margin ?
    • Is there any tool which helps us compute the following ?

  • Hi Vikram,

    We have a very good tool to design the loop filter, please try it. www.ti.com/tool/pllatinumsim-sw.
  • Hi Noel,

    • With the suggested loop bandwidth filter values, we see spurs occasionally at ~6Khz (-50 dBc/Hz) and ~102 KHz (-78 dBc/Hz)  offsets .
    • Can you please suggest ways we can mitigate these spurs which occur occasionally ?

    Regards,

    Vikram  

  • Hi Vikram,

    what is your DEN setting? Please try 8000001. if the spurs still appear, I wonder if this is a power supply issue.