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LMX2595: LMX2595 PHASE NOISE ISSUE

Narendra S10
Intellectual 470 points
Part Number: LMX2595

Support Path: /Product/Development and troubleshooting/

Hello,

We have recently purchased the LMX2595 evaluation board.
In our application we have a requirement to generate 13GHz with a reference frequency of 10MHz... We have kept  PFD to 20MHzusing low noise doubler..We are only measuring a phase noise of -82dB at 10KHz offset.. We are using a very stable OCXO as reference, still we are measuring very high phase noise.... Please advise what could be the problem.... The calculations as per datasheet tells us that the phase noise should be better than -95dB.. Please reply as early as possible.

  • 0
    TI__Expert 5325 points

    Hello Narendra,

    Can you please share your loop filter design?

    The default configuration of the EVM is designed for a PFD update of 200 MHz.

    A quick simulation using PLLatinum Sim yielded a similar result to what you observe.

    An expert for this device will help you to optimize your configuration.

    Best regards,

    Patrick

  • 0 in reply to Patrick Kammermayer
    Intellectual 470 points

    I have not altered the loop filter already assembled in the evaluation board. The device seems to work fine for 100MHz PFD or above... for 10MHz the phase noise is matching the simulation value. I have attached the

    simulation file with the currently assembled default values...Please guide me, where I am going wrong

  • 0 in reply to Narendra S10
    TI__Mastermind 27581 points
    Narenda,

    Two possible reasons for higher phase noise could be:
    1. If you lower the phase detector frequency, the loop filter will be stable, but unoptimized. Even within the loop bandwidth, the phase noise can creep inside and degrade the phase noise.

    2. For the calculations, perhaps you are talking about the PLL noise. For these numbers, the assumption is an infinite loop bandwidth (or at least much wider than the frequency of interest) and a noiseless input reference. I am skeptical that your 10 MHz reference will be clean enough as to not degrade the phase noise inside the loop bandwidth.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Intellectual 470 points

    Hello Dean,

    I have 2 queries.

    1. In the evaluation board datasheet, for the loop filter assembled, the bandwidth mentioned in 285 KHz, but in simulation in PLLatinum why is bandwidth getting simulated ad 49.5Khz... I have attached the 2 images. Please clarify

    The second query is same as earlier.... As per simulation file posted above the phase noise is -94 at 1K and 10K offsets... But practically I am measuring 80 at 10MHz ref.... At 100 MHz ref... the simulation and practical results are matching.... What might be the issue at lower PFD.   Please clarify. I am attaching the phase noise of the source and the measured value of LMX2595 along with TICS PRO settings...

  • 0 in reply to Narendra S10
    TI__Guru* 81400 points
    Hi Naradra,

    In EVM, we used 200MHz fpd, while in your sim, the fpd was 20MHz.
    regarding your second question:
    your fpd is 20MHz, so N divider is very large. as a result, PLL in-band noise will increase.
    for 10MHz reference clock, please use CMOS clock or differential clock. PLL in-band noise depends on the slew rate of the reference clock. The slew rate will be very poor for a 10MHz sine wave clock.
    Is the 10MHz come from a signal generator? The phase noise of a signal generator is usually poor at lower frequency output.
  • 0 in reply to Noel Fung
    Intellectual 470 points
    Hi Noel,
    The 10MHz was from a SIne Wave -- OCXO... I had attached the phase noise specs of the OCXO above... Will try out with a CMOS reference and come back... Thankyou
  • 0 in reply to Narendra S10
    Intellectual 470 points

    Hi Noel,

    The 10MHz was from a SIne Wave -- OCXO... I had attached the phase noise specs of the OCXO above... Will try out with a CMOS reference and come back... Thankyou

  • 0 in reply to Narendra S10
    Intellectual 470 points

    Hi Noel.

    Thankyou  for the suggsetion... With CMOS input the phase noise improved by 10dB. Please suggest the best loop filter  and values  for best phase noise and least spurs for 10 MHz input to generate 13.3GHz... I have attached the phase noise specs of the 10MHz CMOS source.

  • 0 in reply to Narendra S10
    TI__Mastermind 27581 points

    Narendra,

    Based on the phase noise you provided, this will be higher than the PLL noise.

    Attached is a simulation and design to consider