CDCLVPxxxx PECL buffer input rise time to output jitter (additive jitter) relationship

The CDCLVP110x family of devices requires an input rise time of equal or higher than 1.5V/ns. Sometimes this can not be provided in systems. Posted here is a test report showing the output jitter degradation when using a signal source with a slower signal rise time on the CDCLVP1204.

last update: 09/09/2010