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Original question:

ADC12DJ5200RF: JESD204C has crc errors

ADC12DJ5200RF: JESD204C has crc errors

Deeksha M R
Prodigy 110 points
Part Number: ADC12DJ5200RF
Other Parts Discussed in Thread: TIDA-010128, TIDA-01028

Hi,

Wrt my previous question on crc errors in JESD204C data, as per the suggestion provided, after running at lower sampling rates the frequency of occurrence of crc errors has reduced. (P and N are not swapped).

I want be sure that I have not missed any configuration setting. Can you please share configuration files of TIDA-010128 or TIDA-01028?

Can you suggest any work around for this crc errors? 

  • 0
    TI__Mastermind 20541 points

    Hi Deeksha,

    Can you please try writing the following reg writes.

    ADC12DJxx00RF
    0x000  0xB0 // Do soft reset
    delay(0.1)  // 100mSec delay
    0x02B  0x15 // EN_VA11_NOISE_SUPPR
    0x2A2  0x30 // EN_VD11_NOISE_SUPPR
    0x0200 0x00 // Clear JESD_EN (always before CAL_EN)
    0x0061 0x00 // Clear CAL_EN (always after JESD_EN)
    0x0201 0x02 // Set JMODE2
    0x0202 0x03 // Set KM1=3 so K=4
    0x0204 0x01 // Use SYNCSE input, offset binary data, scrambler enabled
    0x0213 0x0F // Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples
    0x0048 0x03 // Set serializer pre-emphasis to 3
    0x0061 0x01 // Set CAL_EN (always before JESD_EN)
    0x0200 0x01 // Set JESD_EN (always after CAL_EN)
    0x006C 0x00 // Set CAL_SOFT_TRIG low to reset calibration state machine
    0x006C 0x01 // Set CAL_SOFT_TRIG high to enable calibration

    In  the above sequence you will need to adjust the JMODE according to your use case.

    Also I would suggest to play with pre-emphasis value and change the value from 0 to 15, and see if the errors go away. Also play with equalization setting on the FPGA side and look at eye diagram and see if get a clean eye. You can check with PRBS test option on ADC to check that. To me this looks like signal integrity issue.  

    0x0048 0x03 // Set serializer pre-emphasis to 3

    Regards,

    Neeraj

  • 0 in reply to Neeraj Gill
    Prodigy 110 points

    Hi,

    I've the same register values used in our ADC configuration file apart from the sequence. Pre-emphasis is done before clearing JESD_EN and CAL_EN.

    JESD data is available with pre-emphasis value of 7 only.

    I've also set,

    0x04F 0x1F 

    0x04D 0x41

    which is for data integrity fix for higher lane rate.

    There is no change in the output. CRC errors still exists.

  • 0 in reply to Deeksha M R
    TI__Mastermind 20541 points

    Hi Deeksha,

    I am closing the thread since the issue was resolved offline.

    Regards,

    Neeraj