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ADS114S06: Switching between 0.03% and 0.3% error for a fixed input

Part Number: ADS114S06

Hey! 

We are currently using ADS114s06 for one of our designs. 

After writing and reading back configuration registers I can say that the communication between the ADC to the controller is fine. Also, we are getting appropriate data output when the input changes.

The issue we are facing is that the error in the raw ADC value is higher in the alternate ADC reset.

That is at the input of 50mV we are expecting to get ~20970 from the ADC, once we will get 20982 which is a reasonable 0.03% error of the full span. But after the power cycle or software reset the ADC, we will get a value in the range of 21080 with an error of 0.33%. Again after doing few a power cycles or the software reset, we go back to a 0.03% error, and again after the power cycle / or ADC reset, it will go bad, so on and so forth.

We first thought that it was some issue with a controller but after resetting the ADC in the main loop we found out that the ADC switches between these to value.

Following is the schematic of ADC 

Some more information:
1. The controller is running at 4.194MHz and SPI communication at 2Mhz though lower or higher frequency didn't help with the issue. 
2. ADC is set for continuous conversion mode, a gain of 32, low latency filter, 2K SPS and uses internal reference and current sources. Also tried with the single short ADC mode but it too didn't help. 

  • Hi Yash,

    Quite often we see these types of issues due to an incomplete POR on a power restart.  What can happen is residual charge still on some device pins (RESET for example) when the supplies collapse but some charge still remains internal to the device.  I have concerns with the RC charge circuit on the RESET pin.  It would be better to let the RESET pin pull high along with the supply.  If the RESET pin is also connected to the micro GPIO, the low time must be long enough so that cap fully discharges and the pin stays low the required timing requirement as given in the datasheet.  You could try removing the capacitor on the RESET pin to see if there is an improvement.

    Another potential issue is the ferrites used on the supplies.  Generally the recommendation is not to use ferrites on the supplies.  Although the ferrites are useful for high frequency noise filtering, the added inductance can cause issues where very short, but larger current demands are required by the ADC.  You could try replacing the ferrites with a 0 Ohm resistors to see if there is improvement.

    As far as sending a reset to the device, are you controlling the RESET pin or sending the RESET command?  If you have not tried both methods, you could try using the method not yet tried to see if you see any differences.

    Are you issuing any calibration commands following startup?  In particular you may want to issue the SFOCAL to remove any ADC offset following power up and reset conditions.

    These are the areas I would suggest investigating.

    Best regards,

    Bob B

  • Thanx Bob,

    It was the issue with the ferrite bead. Removing the fixed it.

  • Here is a temperature vs error graph where we go from 28°C to -35°C blue line, from -35°C to 80°C Red and finally 80°C to ambient yellow. Do you have any more insights?

  • Hi Yash,

    The only thing that I can think of that might show this type of behavior is moisture on the board.  Depending on humidity in the testing environment cooling can create a frost on the circuitry and heating can turn to moisture.

    Best regards,

    Bob B

  • Hey Bob, 

    First of all, thank you for your continued support. 

    We found the issue, we initially thought that the power supply capacitor values were too low for the ADC to work properly.
    After changing the power supply capacitor and having no effect, eventually, we thought we are on edge with the 1uF cap at the Vref pin. So we changed it to a higher value.
    During the process, we found out our assembler screwed up the placement of the capacitor and the 0.1uF capacitor ended up in the place of the 1uF capacitor hence all the problem.
    Apparently, if a lower capacitance value is used at the Vref pin, the reference (sometimes - especially at the high temperature) starts to oscillate and the IC will start to pull the power supply voltage low due to the limited current capability of the supply (<10mA). As we could not scope the power rails at high temperatures in the chamber we never could see it in action. But we confirmed the same by intentionally providing a lower value capacitor. If we had a larger current budget we wouldn't have had this issue.

  • Hi Yash,

    Thanks for the follow up and the resolution.  Hopefully this will help someone else if they see something similar.  The Electrical Characteristics Table on page 9 of the ADS114S06 datasheet shows the range of capacitive load stability for the internal reference.  The minimum load is 1uF and the maximum is 47uF.  Without the proper load it is possible that the reference will oscillate.

    Another important capacitor is between AVDD and AVSS.  The minimum value is 330nF as opposed to the more normal 100nF bypass cap.

    Best regards,

    Bob B