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DAC39J82: Queries on usage and configuration of DAC39J82

Part Number: DAC39J82
Other Parts Discussed in Thread: DAC39J84, , DAC37J82, DAC37J84

Hi, 

We are planning to use DAC39J82 in our application where the following are our requirements (in both cases DAC LO is not used)

  • For Output 1: FDAC is around 2800 MSPS, FDATA is around 1400 MSPS, interpolation factor 2x; the useful spectrum of the signal falls from 0 Hz to around 460 MHz
  • For Output 2: FDAC is around 1000 MSPS, FDATA is around 500/250 MSPS, interpolation factor 2x/4x; the useful spectrum of the signal falls from 0 Hz to around 85 MHz

With regard to this we have few queries as mentioned below:

  1. Is it possible to implement both the outputs mentioned above using a single DAC39J82, assuming the ACLR (Interchannel leakage/coupling) is within the limits? If possible what are the steps and sequences for configuration?

  2. From the Baseband processor to the DAC, Real data samples shall be sent or IQ data samples shall be sent?

    1. If IQ data needs to be sent

      1. For Output 1 generation, the JESD Line rate will be 7 Gbps; LMF = 821, is this a Valid JESD configuration, or are we missing anything here?

      2. As per "Table 9. JESD204B Frame Assembly Byte Representation" in the datasheet, for LMF = 821, Sample positions are given with 3 columns from I0Q0 to I5Q5, shouldn't there be another column indicating the Sample and octets positions(I6Q6 and I7Q7) across Line no 0 to 7? Or is the Diagram/Table correct?

      3. Suppose both the channels of the DAC operate @ 2800 MSPS (2x interpolation), is it possible to meet the Data throughput requirements using JESD( as the calculated line rate is 14 Gbps)? Is it a valid configuration or is there a constraint on Max FDAC/FDATA if we want to use Both the Channels of the DAC (because JESD throughput is the bottleneck here)? What is the configuration of JESD LMF if Both the channels are used?

      4. JESD Parameter M: As per our knowledge, if it's Complex IQ data and one Channel is used then M = 2 corresponds to two Complex convertors; suppose two channels are used with complex IQ data then M = 4, is this convention correct wrt DAC39J82

    2. If Real data needs to be sent

      1. What the conditions/limitations wrt using Interpolation, Mixers, clock, etc?

  3. If FDAC = 2800 MSPS with 2x interpolation, then as per "6.7 AC Electrical Characteristics" then the internal DAC PLL cannot generate this frequency, so do we need to use DACCLKP/N to directly drive the 2800 MHz clock? If Yes, "6.6 Digital Electrical Characteristics" says the Max limit for DACCLKP/N is 2.5 GHz, are there any Errors in the Datasheet wrt this value? Or is there a limitation/conditions on operating @ 2800 MSPS as well?

  4. In Addition to the previous question, if we use FDAC = 2700 MSPS with 2x interpolation, can the internal DAC PLL generate this clock frequency? As per 6.7, it should be able to, but are there any conditions/limitations here? Also any conditions on the Min and Max frequency limits of DACCLKP/N in order to drive DAC PLL?

  5. If we use Xilinx Based JESD IP or any third-party-based standard JESD IPs would this affect the functioning of the DAC? Are there any strict rules on the JESD interface wrt DAC39J82?

Please provide you valuable inputs which would really help us to proceed further.

FYI, using the following datasheet which we got from the TI website: SLASE47 –JANUARY 2015 

Thanks,

Kiran

  • Kiran,

    Before I try to answer all of your questions, please note this part only has one input clock that both DAC's can use. You cannot operate with two different clock frequencies. To get around this, most user's would use a DAC39J84 device which has two separate NCO's that can be set to different frequencies.

    Regards,

    Jim 

  • Hi Jim,

    Thanks for the reply, 

    Could you please provide your valuable feedback for Point no 2 onwards in the above thread? these questions are particularly related to DAC39J82 and are independent of Point no 1.

    Regards,

    Kiran

  • Hi Jim,

    Just another clarification on the two channels of DAC39J84/DAC39J82

    • As mentioned in the original post, we are not using DAC NCO (DAC LO)
    • We wanted different sampling rates @ two channels, one channel with an effective sampling of 1000 MSPS and another with an effective sampling of 2800 MSPS. Will this be possible using either of the DACs mentioned above?

    Thanks,

    Kiran

  • Kiran,

    No this cannot be done. All DAC's in either part use the same input clock. They will all sample at the same rate.

    Regards,

    Jim

  • Kiran,

    Answer below to your earlier questions.

    Regards,

    Jim

    From the Baseband processor to the DAC, Real data samples shall be sent or IQ data samples shall be sent?

     

    If you plan on using both DAC outputs to drive a complex modulator, you will need IQ data. If not, then you can send real data to each DAC.

     

    If IQ data needs to be sent

    For Output 1 generation, the JESD Line rate will be 7 Gbps; LMF = 821, is this a Valid JESD configuration, or are we missing anything here?

     

    If using 1x interpolation and a DAC sample rate of 1400Msps, the line rate will be 7Gbps. If using 2x interpolation and DAC sample rate of 2800Msps, the line rate is also 7Gbps.

     

    As per "Table 9. JESD204B Frame Assembly Byte Representation" in the datasheet, for LMF = 821, Sample positions are given with 3 columns from I0Q0 to I5Q5shouldn't there be another column indicating the Sample and octets positions(I6Q6 and I7Q7) across Line no 0 to 7? Or is the Diagram/Table correct?

     

    The table is actually showing 6 samples of data. This is confusing as the table should have only shown the 1st column as the number of samples per frame = 2 (S parameter in LMFS = 8212).

     

    Suppose both the channels of the DAC operate @ 2800 MSPS (2x interpolation), is it possible to meet the Data throughput requirements using JESD( as the calculated line rate is 14 Gbps)? Is it a valid configuration or is there a constraint on Max FDAC/FDATA if we want to use Both the Channels of the DAC (because JESD throughput is the bottleneck here)? What is the configuration of JESD LMF if Both the channels are used?

     

    Max line rate is 12.5Gbps per the standard.

     

    JESD Parameter M: As per our knowledge, if it's Complex IQ data and one Channel is used then M = 2 corresponds to two Complex convertors; suppose two channels are used with complex IQ data then M = 4, is this convention correct wrt DAC39J82

    If Real data needs to be sent

    What the conditions/limitations wrt using Interpolation, Mixers, clock, etc?

     

    This device only has 2 DAC’s and M =2 when using both channels. M cannot be greater than 2. The complex mixer will send out I and Q data. Most customers send I data to one DAC and Q data to the other DAC for a complex output.

     

     

    If FDAC = 2800 MSPS with 2x interpolation, then as per "6.7 AC Electrical Characteristics" then the internal DAC PLL cannot generate this frequency, so do we need to use DACCLKP/N to directly drive the 2800 MHz clock? If Yes, "6.6 Digital Electrical Characteristics" says the Max limit for DACCLKP/N is 2.5 GHz, are there any Errors in the Datasheet wrt this value? Or is there a limitation/conditions on operating @ 2800 MSPS as well?

     

     

    This is a typo in the data sheet. The max external clock is 2800Msps for the DAC39J82.

    The ranges of the two internal VCO’s are 4.44-5.6GHz and 3.7-4.66GHz. The DAC can operate with the internal PLL sampling at 2.8GHz when using the upper limit of the higher VCO. This would be operating at 5.6GHZ and divided by 2 to generate 2.8GHz.

     

    In Addition to the previous question, if we use FDAC = 2700 MSPS with 2x interpolation, can the internal DAC PLL generate this clock frequency? As per 6.7, it should be able to, but are there any conditions/limitations here? Also any conditions on the Min and Max frequency limits of DACCLKP/N in order to drive DAC PLL?

     

    See attached document.

     

     

    If we use Xilinx Based JESD IP or any third-party-based standard JESD IPs would this affect the functioning of the DAC? Are there any strict rules on the JESD interface wrt DAC39J82?

     

    Must use subclass 1 mode which requires SYSREF No other rules that I am aware of other than this.

    8640.DAC38J84 Clock, PLL and SERDES Configuration.docx

  • Hi Jim,

    Thanks a lot for your inputs, we will go through the document for getting clarity on Clock, Sysref, and PLLS. Could you please help us with the following queries

    1. If we are using Interpolation by 2x (any factor greater than 1x) and not using DAC LO/NCO, then from the baseband processor(FPGA) to the DAC, do we need to provide Complex IQ Data or Real data? Some DAC circuits require Complex IQ data for Signal processing like Mixing, Interpolation, etc. just wanted to have this clarity.

    2. Suppose if we want to use complex mixers, both the channels operating @ 2800 & 2x interpolation factor, then due to limitations in the JESD line rate, we won't be able to use this DAC (DAC39J82) as it would require a JESD line rate of 14 Gbps each, is this correct?

    Based on the answer to the above queries, we might be able to determine the Sampling V/s Channel usage V/s JESD Line-rate, etc.

    Thanks,
    Kiran

  • Kiran,

    For #1, you can use real or complex data.

    For #2, the data rate to the DAC will be 1400Msps which is a line rate of 7Gbps. The DAC would be sampling at 2800Msps. This is assuming you are using 8 lanes. If you were to only use 4 lanes, then the line rate would be 14Gbps. See the numbers from the DAC39J82EVM GUI below.

    Jim

  • Hi Jim,

    Thanks for the quick reply..

    For #2, using complex mixers @ both the channels isn't the required JESD line rate = 1400*(16+16)*2*1.25/8 = 14 Gbps ?

    Parameters used for calculation in the order : FDATA = 1400 MSPS, (16 bit I data + 16 bit Q) data per channel, Number of channels = 2, 8b/10b factor  = 1.25, No of JESD lines = 8 

    Regards,

    Kiran

  • Hi Jim,

    Our ultimate goal is to finalize DAC chips suiting our application needs as mentioned below.


    Terminology: FDATA is the rate at which the DATA samples are sent from FPGA to DAC; FDAC is the DAC Sampling rates which is = FDATA x Interpolation factor

    In our application, we have the following requirements,

    • Output 1 : FDAC = 2800 MSPS, FDATA = 1400 MSPS, interpolation factor 2x; the useful spectrum of the signal falls from 0 Hz to around 460 MHz

    • Output 2 : FDAC = 2800 MSPS, FDATA = 1400 MSPS, interpolation factor 2x; the useful spectrum of the signal falls from 0 Hz to around 400 MHz

    • Output 3 : FDAC = 1000 MSPS, FDATA = 500/250 MSPS, interpolation factor 2x/4x; the useful spectrum of the signal falls from 0 Hz to around 85 MHz

    We would like to use a Minimal number of DAC chips in order to save on board real estate. So we don't want to use 3 number of DACs, any dual channel DAC which could meet our requirements mentioned (along with meeting JESD/Data transfer limits) above would help us a lot. Could you please provide your suggestion for the possible DAC part# and the method of using them?

    Thanks,
    Kiran

  • Kiran,

    Use one DAC39J82 for outputs 1 and 2 and one DAC37J82 for output 3. The DAC37J82 is rated up to 1.6Gsps and will be cheaper than the DAC39J82.

    Regards,

    Jim

  • Hi Jim,

    Thanks for taking your time in answering our queries, we will study DAC37J82 as well, hope that the architecture and terminologies remain almost similar to DAC39J82.

    Regarding DAC39J82,

    1. To clarify our final point, If 2 channels are needed for Individual outputs @ 2800 MSPS along with interpolation of 2x on both the channels and without using DAC NCO, can DAC work with REAL DATA samples only? So can we say that the interpolation block on each channel path doesn't require Complex data?

    2. In the above case, if we also need the Complex mixer, then the DAC can only implement the functionality of One output and it requires COMPLEX I Q data from the baseband processor, is this correct? If the DAC can meet the functionalities of two-channel outputs then whats the JESD line rate (with complex data required on both the channels) and what could be the values of configuration parameters like LMFS?

    To come to a conclusion on DAC39J82, it would be helpful if you could provide your inputs on the above two questions.

    Thanks,

    Kiran

  • Hi Jim,

    I forgot to mention another most important condition, 

    • Output 1 and Output 2 cannot be on the same DAC, because of the inter-channel leakage issue and closer output spectrum
    • Output 1 and Output 3 can be on the same DAC

    Regards,

    Kiran

  • Then you will need to use two DAC39J82's and one DAC37J82. Output 1 and 3 cannot come from same device.

  • Hi Jim,

    Thanks for the reply again, after a few studies and analysis of the DAC37J82/DAC37J84 datasheet, come across the following understanding

    1. For Interpolation > 1x, it doesn't need Complex IQ Data, it can work with Real data samples

    2.  If we don't use NCO Mixers in DAC37J82, it Can generate

      1. Output_i : 1x or Interpolated(2x to 16x) output corresponding to first channel data samples (Real data)

      2. Output_ii : 1x or Interpolated(2x to 16x) output corresponding to Second channel data samples (Real data)

      3. DACA, DACB, DACC, DACD can be configured to select any of the outputs

    3. If we need to use DAC LO/NCO Mixers then DAC requires Complex IQ data

    4. If we need Mixers on Both the channels then

      1. DAC37J82 cannot handle it, it has only one Complex Mixer.

        1. DAC has only 2 outputs, the Real part of the Mixer output and the Imaginary part of the Mixer output; DACA, DACB, DACC, DACD can be configured to select any outputs of the Mixer.

      2. DAC37J84 Can be used, it has two Complex Mixers. Outputs based on the default configuration of pathX_out_sel register bits setting

        1. DACAREAL part Mixer 1 output, DACBImaginary part Mixer 1 output 

        2. DACC: REAL part Mixer 2 output, DACD: Imaginary part Mixer 2 output

    5. With DAC37J82, 2 Channel Real data, Max FDATA = 1400 MSPS resulting in JESD line rate of 7 Gbps (8 lines used); Same sampling and JESD rate applies to One channel Complex data, with Real and imaginary Mixer o/ps

    6.  WIth DAC37J84

      1. With 4 Channel Real data, Max FDATA = 1250 MSPS resulting in JESD line rate of 12.5 Gbps (8 lines used); Same rates apply to 2 channel complex data 

      2. 1 channel complex or 2 channel real data, sampling and JESD rate same as point no 5 mentioned above

    Are these points accurate, please suggest so that it would really help us to proceed with the design. 

    Thanks,

    Kiran

  • Kiran,

    See attached.

    Regards,

    Jim

    answers.docx