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DAC53608: Clarification of Power-on-Reset function

Part Number: DAC53608

I do not understand how the POR circuit operates on the DAC53608?

The datasheet states that for a POR to occur, VDD must be less than 0.7V for at least 1ms.

Is this referring to the speed of the VDD rise time?

Can I also ask if the CLR pin operation is identical to the POR function?

Thanks

Robert

  • Hi,

    If you want to have POR to happen after every power up, it has to remain below 0.7V for min 1ms. In a way this defines the speed of the VDD rise time. Now after up, lets say, accidentally power supply drops to 0.6V and immediately comes back ( power supply droop time was less than 1ms), POR may not happen.

    CLR pin act as an asynchronous input to the DAC, meaning when its pulled low, all the DAC contents ( only the data registers and its buffers) will be loaded with zero codes. It doesn't have any effect on other registers such as DEVICE_CONFIG, TRIGGER.

    POR will clear everything and DAC will be in its default state while CLR has effect only on the DAC_DATA registers

    Regards,

    AK

  • Hi AK

    Thanks for a really good explanation.  May I ask one more question please.

    Do you know what actually triggers the POR event?  Does the device detect a minimum voltage level above 0V in order to start the 1ms count - after which time the POR occurs (assuming that the 0.7V level is not breached during that 1ms interval).

    So another way to ask: At what minimum voltage level does the 1ms timer (to trigger the POR) begin?

    Regards

    Robert

  • Hi,

    Let me check this information in the design documentation and gets back to you.

    Regards,

    AK

  • Hi Robert,

    Condition of below 0.7V for 1ms is written because many customers design bad power supplies which dips way below valid voltage for short duration. And in such a case sometimes device gets reset, some other times it does not. This is the reason we say that if the supply dips below valid supply, customer should take supply below 0.7V and keep it at that state for 1ms to be sure that POR/reset event takes place.

     But for initial boot-up this condition is already satisfied because the voltage ramp starts from 0V, and the device would have been in 0V state for >1ms before ramp-up

    Hope this clarifies your question.

    Regards,

    AK