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ADC3244E: about ADC3244E questions

Part Number: ADC3244E
Other Parts Discussed in Thread: ADC3244, , DATACONVERTERPRO-SW

Hi team,

Please help to answer the following questions about ADC3244E evaluation board:

1. The maximum sampling rate of ADC3244E is 125msps, and the estimated total transmission rate should be 2gbps. It supports serial LVDS interface, but it is found that the upper limit of serial LVDS interface rate is 1.0gbps, which is less than 2gbps. Will it affect data transmission?

2. Can ADC3244E evaluation board be connected with FPGA development board supporting LVDS interface? Is there a relevant interface? Please elaborate.

3. The data transmission of ADC3244E evaluation board is (1) real-time transmission? Or (2) cache the collected data in the register of ADC evaluation board, and then transfer the cached data out at a certain rate?

4. For different ADCs, there are different interface types. What are the differences among LVDS, parallel LVDS, serial LVDS, DDR LVDS and QDR LVDS?

Thanks a lot.

Best regards,

  • Hi Zhonghui,

    1. The maximum sampling rate of ADC3244E is 125msps, and the estimated total transmission rate should be 2gbps. It supports serial LVDS interface, but it is found that the upper limit of serial LVDS interface rate is 1.0gbps, which is less than 2gbps. Will it affect data transmission?

    The ADC3244 family uses serial LVDS, so if we consider the 2 Wire mode (see page 18 of data sheet), the output data is toggling at 3.5 * the sample rate (125M * 3.5 = 437.5 MHz). Since this is a DDR interface, we must multiply 437.5 MHz by 2 to obtain the actual data rate (437.5 MHz * 2 = 875 Mbps). This is because DDR "latches" the data on both rising and falling edges of the clock [hence Double Data Rate (DDR)].

    2. Can ADC3244E evaluation board be connected with FPGA development board supporting LVDS interface? Is there a relevant interface? Please elaborate.

    Yes, we support the ADC3244E with the ADC3244EVM, which then connects to the TSW1400EVM FPGA capture card. The Serial LVDS interface is used for evaluation.

    3. The data transmission of ADC3244E evaluation board is (1) real-time transmission? Or (2) cache the collected data in the register of ADC evaluation board, and then transfer the cached data out at a certain rate?

    The TSW1400EVM does not support real-time transmission, but captures a set of samples (configurable) and displays the captured samples in an FFT or in the time domain. Please see HSDC Pro software user's guide (DATACONVERTERPRO-SW) for more information.

    4. For different ADCs, there are different interface types. What are the differences among LVDS, parallel LVDS, serial LVDS, DDR LVDS and QDR LVDS?

    Serial LVDS is what the ADC3244E uses. The data is packed onto one or two wires/outputs, and is transmitted at a higher rate than that of the sampling rate. Similar to something like a high speed SPI interface.

    Parallel LVDS (DDR) allows for two bits to be represented at each data wire/output, and is at the same frequency as the sample clock. This implementation requires more output pins than the Serial LVDS.

    For a better explanation of the QDR interface, please see page 42/43 of this data sheet https://www.ti.com/lit/ds/symlink/ads42lb69.pdf?ts=1621518307769&ref_url=https%253A%252F%252Fwww.google.com%252F 

    Best Regards,

    Dan

  • Hi DBrock,

    Thank you for your detail answer.

    Best regards,