ADS54J64: ADS54J64

Hi Jim,

I am trying to evaluate ADS54J64 with ‘KC705 + ADS54J64EVM + TSW14J10EVM’

Combination. But I am having a trouble with the operation. It could be my configuration problem.

I want to use this ADC for the LIDAR application and basically I want to capture Gaussian pulse with DDC bypass mode.

Before the real signal testing I tried the Test Pattern test first but I couldn’t make it working. Following is the configuration I made:

ADS54J64 GUI:

1. From ‘INTRO’ I selected ‘Fclk=983.04MHz’.

Note: I could only see D3 (PLL2 lock indicator) was ON.

2. From ‘ADS58J46 Mode’ I selected DDC Mode 8.

3. From ‘ADS58J46 Other’ I configured parameters as following.

Data Test Patterns:

• Test Pattern: Ramp Pattern
• Test Pattern Enable: Ch.A, Ch.B, Ch.C, Ch.D,

JESD204B:

• K28.5 Link layer Pattern
• Use SYNCbCD for ch.AB control

HSDC Pro:

• I selected ‘FTSCNUS-TSW14J10KC705.
• I selected ‘ADS54J66_LMF_4421’. (There is no ADS54J64 in ADC list.)
• I put ‘ADC Output Date Rate’ as 491.52.

I downloaded ‘TSW14J10_KC705.svf’. I selected the ‘Time Domain’ for Test Selection. When I clicked ‘Capture’, there was no ‘Ramp signal’ on the HSDC Pro screen. I could see D15 was stuck to ‘1’ and the rest remained ‘0’. GPIO LED status on KC705 was as follows:

0 -ON

1 -OFF

2 - OFF

3 - ON

4 - OFF

5 - Blinking

6 - OFF

7 – Blinking

Please inform me what should be done to make it working. Thanks.

Young,

The KC705 may not work at a serdes rate of 9.8304Gbps as the transceivers on the FPGA have a dead spot between 8G and 9.8G. We have never tested the ADS54J64 with this setup. I would suggest trying to use the ADS54J64 setup like you have been doing but use a sample clock of 491.52MHz just to verify you can get the setup working. After loading the ADC and LMK per the User's Guide, go to the LMK04828 Clock Output tab and change the CLKout 2 and 3 DCLK Divider to 6. Next since the FPGA firmware requires a core clock, unselect the Group Powerdown on CLKout 12 and 13. On this same clock, set the DCLK divider to 24 and the DCLK type to LVDS. In the SYSREF and SYNC tab, set the SYSREF divider to 192. In HSDC Pro, use the same ini file but set the ADC data rate to 245.76Msps.

If the FPGA is receiving the three required clocks, LED's 5, 6 and 7 should all be blinking. If this works, you next trying to increase the sample rate.

Regards,

Jim

Hi Jim,

Thanks for the prompt response. I followed your instruction and I got LED5, 6 and 7 were all blinking. But I had a following Time Out Error when I clicked the Capture button.

‘Read DDR to file TIMED_OUT_ERROR Time Out error’

Regards,

Young

Young,

Can you run Chipscope and monitor the LMFC, SYNC, SYSREF, and the serdes lanes inside the FPGA? If not, try and probe the SYNC signal on the ADC EVM and verify it is high after clicking on the capture button. The link will never get established without SYNC going high and staying high.

Regards,

Jim

Hi Jim,

I'd like to use Chipscope. But where is the design?

Thanks,

Young

Jim,

After I downloaded ‘TSW14J10_KC705.svf’, I tried to open the hw_target from Vivado. But it showed error: There is no current hw_target.

Young,

This TSW14J10 firmware is old and not optimized for normal operation. It was designed to be used with the TI HSDC Pro GUI to allow customers to do a quick evaluation of the TI part under test. It is not firmware one would use with a end product and it does not allow you to use Chipscope either if I remember correctly. I would highly suggest you create your own firmware using examples provided by Xilinx as one option. Another option is to apply for free TI JESD204C IP which has documentation as well as example reference designs for Xilinx FPGA's.  You can apply for this IP by going to the following link:  

https://www.ti.com/tool/TI-JESD204-IP

Regards,

Jim

Hi Jim,

I applied that IP before and it was approved. But I didn't downloaded because I thought I could make it with that TSW14J10 firmware. I should have downloaded that IP. Now the case (CS0529829) is closed. So I have to re-apply.

Thanks,

Young

Young,

With the TI IP, you do not need the TSW14J10EVM. You can plug the ADC EVM directly into the KC705.

Regards,

Jim

Hi Jim,

I requested that IP last Friday. Is there any way that I can check the status of it?

Thanks,

Young,

This usually takes a few days. After the customer is approved an email will be sent out.

Regards,

Jim

Hi Jim,Table.xlsx

After I synthesized TI_204C_IP_ref design targeting KCU105 evm , I got some critical errors. And it failed to generate the bit file. Please review attached table.xlsx file.

Another question is if I can use the constraints file which is in zcu102_8b10b folder for this target. It is complaining and looks like I need to generate the constraints file for KCU105.

Thanks,

Young

Hi Jim,

I am using Vivado2020.1. I tried for targeting KC705, but the same warning message as KCU105.

[Netlist 29-180] Cell 'IBUFDS_GTE4' is not a supported primitive for kintexu part: xcku040-ffva1156-2-e. Instance 'TI_IP_inst/jesd_ip_gen.j8b10b_inst/xcvr_gen.xcvr_inst/genblk1[0].IBUFDS_GTE4_INST' will be treated as a black box, not an architecture primitive ["C:/work/SBL_mini/TI204C-IP-Release-v1.10-LATEST/reference_designs/zcu102_8b10b/rtl/gth_8b10b_rxtx.sv":82]
[Netlist 29-180] Cell 'IBUFDS_GTE4' is not a supported primitive for kintexu part: xcku040-ffva1156-2-e. Instance 'TI_IP_inst/jesd_ip_gen.j8b10b_inst/xcvr_gen.xcvr_inst/genblk1[0].IBUFDS_GTE4_INST' will be treated as a black box, not an architecture primitive ["C:/work/SBL_mini/TI204C-IP-Release-v1.10-LATEST/reference_designs/zcu102_8b10b/rtl/gth_8b10b_rxtx.sv":82]
 

Young,

It appears you are using the wrong reference design. The zc706 design should be used as the starting point.

Regards,

Jim 

Hi Jim,

I tried the zc706 design and I got critical warning messages including timing failure. I continued to try mapping that design to kc705. And I got drc failure due to unconstrainted port on the top up critical warning messages. As I said I am using Vivado 2020.1. Is anything got to do with the Vivado version. TI204c_IP-userguide specifies Vivado (2019.x or higher), though.

Thanks,

Youngzc706_critical_warnings.xlsxkc705_log_file.txt

Young,

It appears you are trying a blind port of the ZC706 reference design to the KC705, which won’t work. A reference design is meant to be a starting point, and it should be modified to match the new FPGA. We noticed that most of the design pins aren’t assigned to FPGA pins.

Regards,

Jim

Hi Jim,

I re-tried ZC706 reference design only (not mapping to KC705) and I got timing failure. Please find the attached timing report. This time I used Vivado 2019.2 to find out if this issue was caused by different Vivado version. But it is not.

Thanks,

Young  

Not sure that report file was uploaded.

No file was attached

TI_204c_IP_ref_timing_summary_routed.txt.rpt.txtHi Jim, I uploaded it again. Thanks.

Hi Jim,

I could be able to generate the bit file for KC705 but I had the timing failure. I had a timing failure with even ref design itself. I already uploaded timing summary report about a week ago.

Currently I am working on some other project. I will revisit this issue later.

Thanks,

Young

Young,

When looking at your error report, it appears you are not mapping the pins correctly. This is not a timing issue. Can you do the following:

1. Recompile the example design as is to make sure they are no Viviado version or reference design issues.

2. Change the pin mapping from the ZC706 design and target the KC705 design. Please let us know exactly how you are doing this so we can verify the steps taken are correct.

Regards,

Jim

Jim,

I am not sure whether you got the right file. The file I uploaded (TI_204c_IP_ref_timing_summary_routed.txt.rpt) is from compilation of original ZC706 ref design with accompanied constraint file. It wasn't from KC705. 

Thanks,

Young 

Young,

So this was the original reference design and you did not change anything, correct? 

Jim

That is correct. I didn't change anything.

Thanks,

Young

Young,

All of the reference designs were compiled with version 2019.1. By any chance can you try using this version to see if the timing errors clear?

Jim 

Jim,

I tried it with 2019.2. TI204c_IP-userguide specifies Vivado (2019.x or higher). As I said I am working on some other project now. I will try 2019.1 later.

Thanks,

Young