• State TI Thinks Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 5 answers
  • Subscribers 45 subscribers
  • Views 216 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS124S08: Design feedback

Jonathan Craig
Prodigy 100 points
Part Number: ADS124S08

Hello,

I have created a design using the ADS124S08 ADC for sampling 4x PT1000 RTDs. We plan on sampling each RTD at 10sps so a total sampling rate of 40SPS.

The temperature range of the environment will be from -20 to 60 degrees C and I plan on using 1mA IDAC current. As AVDD is 3.3V I do not currently plan on using the PGA gain.

Would it be possible to check if my design has been done correctly? I have tried to follow the data sheet and the available TI Cook books..

Any help and feedback with this is very much appreciated.

Kind regards8662.ADC.pdf

  • 0
    TI__Guru** 112895 points

    Hi Jonathan,

    Welcome to the E2E forum!  I will make the assumption that 4-wire RTDs will be used.  I don't see any issues with the schematic to prevent intended operation, however there are a few considerations. 

    The first is the IDAC compliance voltage, and your margin is getting small as you approach 60 deg C.  The second consideration is with respect to input protection.  The need for additional input protection depends on the system and any exposure to EMI/RFI and sensitivity to ESD.  Your system must prevent exceeding the absolute maximum ratings given in the table for the ADS124S08.  One way that the ratings can be exceeded is by current flowing through the input pin by 10mA or more.  If an overvoltage condition should take place where current can potentially flow through the ESD diode structure of the ADS124S08, the current must be limited.  In many cases the input filter resistors will limit the current, but additional protection may be required such as TVS voltage clamps.  Where your circuit is most vulnerable is the IDAC pins and adding any protection here will affect meeting the compliance voltage.

    The third consideration is timing.  When switching from one RTD to the next, you need to consider any analog settling time required in the current path.  Also, there is some latency in the digital filter that must also be considered.  The first conversion after a mux change will have some latency as shown in table 13 on page 42 of the ADS124S08 datasheet.  Also note that there is additional delay beyond what is shown in the table as stated in note 3 under the table.

    Best regards,

    Bob B 

  • 0 in reply to Bob Benjamin
    Prodigy 100 points

    Hi Bob, thank you! yes you are correct i will be using 4x 4 wire RTDs, sorry I should have mentioned that.

    In order to reduce the chances of getting close to the compliance voltage of the IDAC, would reducing the excitation current to 500uA and using a gain of 2 be sensible?

    If i do that could you advise if the noise level of the measurement would be affected greatly as I reduce excitation current? I can't see anything in the data sheet, however i may have missed it.

    Would i be able to keep my schematic as it is if i reduced excitation current to 500uA? As in would my reference resistor or filter resistor values need to change at all? From going through the cookbook I don't think it would..

    Could i also confirm that i have understood the filtering correctly. As i will be sampling at 40SPS i have selected my differential frequency to be >400Hz and my common mode frequency to be 20x greater than differential. I have then used the equations provided to calculate my capacitors. I have use the same frequency at the reference input as the differential input and calculated capacitor values to achieve that.

    Thanks a lot for your help with this. I will have a read up on timing to make sure i understand it all correctly. Would all the timing requirements be handled in software?

    Kind regards,

    Jonathan

  • 0 in reply to Jonathan Craig
    TI__Guru** 112895 points

    Hi Jonathan,

    • If you reduce the current to 500uA, then you will increase the range relative to the IDAC compliance, however you will not be able to increase the gain without increasing the reference resistor value.  Even though you reduced the current, the ratio of the RTD to Rref remains the same.
    • It is difficult to predict the overall noise in your measurement as this will be affected by external noise sources.  Even with the IDAC at 1mA will not guarantee a specific signal-to-noise ratio (SNR).  With respect to the ADC itself, you can determine the noise based on the noise voltage tables in the datasheet.  The ADC noise voltage will be what affects the overall measurement.  So the ADC noise is the same, and reducing the input voltage will lower the SNR.
    • You would not need to change the filter values.
    • The input filtering serves two purposes.  The first is antialiasing and the second is external noise filtering.  The ADS124S08 is an oversampling ADC with a modulator rate of 256kHz.  The input signal is primarily dc.  You don't need to be that concerned with hitting a specific input filtering with respect to data rate as long as your filter is adequate relative to the modulator rate.  That is why most Delta-Sigma devices only require a simple RC 1st order filter for antialiasing. Filtering with respect to the data rate is a good practice, but will most likely not increase performance and just increases analog settling.  If external noise filtering is required, then that may be the bigger issue to design around.
    • There is a delay functionality built into the ADS124S08 to automatically adjust for analog settling when switching the mux.  These are the DELAY setting bits in the GAIN register.  The default setting is 14 tmod periods.  There are various delay options and can be extended up to 4096 tmod periods.  The advantage here is consistency in every measurement period and also eliminating a timer requirement by the micro.

    Best regards,

    Bob B 

  • 0 in reply to Bob Benjamin
    Prodigy 100 points

    Thanks for the response Bob.

    Right of course, didn't take into account the current through the reference resistor.

    So to clarify with regards to the input filtering, when the cookbook design mentions setting differential frequency values to be 10x the data rate do they mean the sample per second rate? And for faster measurements we might want to try and keep the 3db point lower due to analog settling time? I see it mentions this in the RTD Ratiometric Measurements and Filtering document.

    We also want to try and match the frequency bandwidth of the differential inputs to the ADC and to the reference resistor? So if i have 450hz bandwidth on the analog inputs i would need the same on the reference input?

    Thanks for your help with this.

  • 0 in reply to Jonathan Craig
    TI__Guru** 112895 points

    Hi Jonathan,

    Yes the filter discussion refers to the data rate (sps) for 10x.  In general you would make a compromise between settling time and desired filter cutoff.  For ratiometric measurements you try to match the filter response of the analog input to the reference input as much as possible, but this is not always as practical as it sounds.  The RTD itself is a part of the filtering and it is changing.  Also, filter components have a variety of tolerances so again this is a compromise as to cost and level of precision required.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 100 points

    Hi Bob,

    Thanks for getting back to me.

    I've updated the design for a 500uA excitation current  with a gain of 2 and a ~200Hz filter cut off. I've extended the operation range to -20 to 80 degrees (921 to 1309 ohms for the PT1000)

    The new values are:

     -3K3 reference resistors

     - 56nf differential cap

    - 6.2K differential input resistor on adc input

    -5.6nf common mode cap on the adc input

    -5K6 reference input  filter resistor

    - 91nf Reference input filter capacitor

    Can i check that the updated design would operate correctly?

    Thanks again

    Jonathan

  • 0 in reply to Jonathan Craig
    TI__Guru** 112895 points

    Hi Jonathan,

    That configuration appears to be ok.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 100 points

    Hi Bob,

    Thanks for your help.

    I've once last question. If we are sampling 4x RTDs while multiplexing the IDAC through them sequentially and we want to achieve a sample rate of 10SPS at each RTD, do we need to sample at 40SPS or at 10SPS?

    Thanks again,

    Jonathan

  • 0 in reply to Jonathan Craig
    TI__Guru** 112895 points

    Hi Jonathan,

    The sps rate as shown in the datasheet is a nominal rate for a conversion period.  When cycling through the mux where you want 4 separate measurements to take place in a 100ms window you would need to adjust the data rate for the conversion accordingly.  The result is 100ms/4 or one complete measurement every 25ms.

    From Table 13 in the ADS124S08 datasheet we see the low-latency filter times for the various nominal data rates.  We need to select a data rate that is 25ms or faster.  The length of time is shown in the ms column for the first data conversion times.  You will notice that there is no 40sps settings available, so the next closest time would be at the 50sps data rate.

    Best regards,

    Bob B