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ADS1293: Sampling rate differs from datasheet

Part Number: ADS1293

Hi!

We're using the ADS1293 and have it set up to do output data at 267HZ but the DRDY pin is just toggling at 260Hz. Is there any reason for this/is this expected behavior? 

  • Hi Konrad,

    Please let me verify this with the EVM and get back to you. Is it possible to share the complete device register setting?

    Thanks

    -TC

  • Hi Konrad,

    I have tested a few digital filters setting to get the ODR of 267Hz with an internal oscillator. I was able to observe the ODR of 267Hz on my logic analyzer. Please see the plots below for reference.

    SDM Running at 102.4kHz.

    R1=4, R2=6, R3=16

    R1=4, R2=8, R3=12

    R1=2, R2=6, R3=32

    Equation 5 in the datasheet shows ODR is derived from the clock frequency of the modulator and the digital filter setup (R1, R2, and R3). I would verify the internal clock frequency to the device is correct by probing the device's CLK pin.

    Thanks

    -TC

  • Thanks! The internal clock is at 400kHz, is that the correct value?

  • Hi Konrad,

    Thanks for the information.

    The typical CLK operating condition for the ADS1293 is 409.6kHz (see Section 8.3.19 of the datasheet) with an external 4.096MHz crystal. If the device runs at an internal clock of 400kHz, then the ODR you set for 267Hz will be equivalent to 260.4Hz.

    ODR = 400kHz/4/384 = 260.4Hz (R1=4, R2=6,R3=16)

    Thanks

    -TC