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ADS1256: Behavior of DRDY

Part Number: ADS1256

I'm using the method described in the datasheet Figure 19 to cycle the ADS1256 Input Multiplexer. The below oscilloscope capture shows 3 bytes WREG, 1 byte SYNC, 1 byte WAKEUP and 1 byte RDATA commands followed by the acquisition of 3 bytes sample data. The behavior of DRDY doesn't correspond to the figure in the datasheet. Why is DRDY going high two times before going high "for real" and indicating that a conversion is ongoing?

/F

  • Hi Fredda,

    What is the data rate you are sampling at and what is the master clock rate for your system?

    -Bryan

  • The master clock is running at 10 MHz and SCLK is running at 1 MHz. I think the DRATE register was set to 11110000 so that the averager is bypassed and the sampling rate is 39 062.5 MHz. Can it simply be so that the short DRDY pulses are indicating conversions and that new samples are ready? Yes, I guess so... The sampling period is 25.6 us and that's the distance between the two pulses.

    /F

  • Hi Fredda,

    Indeed that is what is happening, but I needed to know your MCLK and data rate speeds in order to confirm.

    Those pulses are indicating that data is ready to sample, and you are just missing the data read back for each.

    So you either need to speed up your communication or slow down your data rate.

    -Bryan

  • Thanks for confirming what I suspected. I normally have DRATE set for 6000 averages so it's not a problem.