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ADS1282: Data readout

Jay Prizant
Prodigy 40 points
Part Number: ADS1282

In the section on Data Format it says "If desired the readback may be stopped at 24 bits." is this done by simply having the user logic stop providing SCLK pulses after 24 pulses? And then wait for the next drdyn assertion for the next sample? Jay 

  • 0
    TI__Mastermind 44550 points

    Hi ,

    Correct, you stop sending SCLKs and only regard the most significant 24-bits if you prefer. The least significant bits are noisy especially at the higher data rates. Unless you plan to do additional post-processing or averaging you don't lose much information from ignoring the least significant byte.

    Some additional considerations when operating the ADS1282 like this...

    • I would recommend using RDATAC mode when doing this so that /DRDY automatically goes low once the next conversion completes. In SDATAC mode an RDATA command is required to enable the /DRDY interrupt.
       
    • The filter mode (SINC + FIR, or SINC-only) does have a small effect on the output data format... In FIR filter mode the 31-bit data is left-aligned in the 32-bit word; in SINC-only mode it is right-aligned. Therefore, if you're using the SINC filter mode you might consider clocking out the first 25-bits (if you have an FPGA or MCU that allows for this frame-length) to get 24-bits of data. Otherwise, you'll only have 23-bits.
       

    Best regards,
    Chris