ADS4222: how to set clock input from FPGA

Jim,

So what solution do you recommend for ADS4222 clock input? Any reference schematic or clock component?

Any simple solution recommended? 

Does it work with oscillator?

My application is 50M sample rate

What's the criteria of acceptable?

Any guideline for me to check or analyze it?

If the part will meet your SNR, ENOB, and or SFDR specs if you have any. The documents I sent will help you calculate the expected SNR performance based on the noise of your clock source.

Hi Jim,

My application is to design a circuit to capture voltage pulse (such as, 100ns, 1us..)  like oscilloscope.

I just care about the accuracy and sample rate. 

I don't know how much is SNR = 70 dBFS impact for me. So I can not define it.

Do you have generic advice? Should I use clock generator IC or such VCOX or FPGA pll output?

It's big job and cost to use clock jitter cleaner. I hope to make it simple.

Good idea, thanks! Just look back the clock jitter documents. FPGA jitter is about 400ps, and clock generator IC is about 1 ps. 

For my application, I use the ads4222 to read the voltage every 20ns to draw a line to track the voltage change.

1) first sample start at 0ns

2) second sample should be at 20ns +/- 400ps in case use of FPGA as clock input.  

Early or later about 400ps to read the adc value, it's fine to draw voltage change curve.

So, I conclude FPGA output as clock is ok.

Do you think my analysis is right?

One more ideas, if I use clock oscillator, can I use one oscillator to driver 2xADS4222? 

Any potential issue?

clock_k_e-1388782.pdf

Not sure. This depends on the length of the pulse, how many times it will get sampled and when it gets sampled. Since it appears the clock source and pulse are not synchronized, the end result could be effected by all of these conditions.

You may get reflections on the clock lines depending on how they are routed. i would suggest using a 1:2 buffer to be on the safe side.

if clock buffer used, then I don't need to use oscillator. Just FPGA output clock -> clock buffer. It will give enough low jitter, right?

No, you still need the oscillator. The buffer just makes duplicate copies of a single input. See attached data sheet for a buffer that could work for you. It does not clean up the signal. It will add some jitter but very minimal.

Cdcv304.pdf

If clock buffer doesn't help on the overall jitter. It makes no sense for me to use it. Clock buffer price is much higher than oscillator. Then I can use 2 pcs separate oscillator to drive 2 pcs ADS4222.