TSW54J60EVM: Understand the raw data format received on the FPGA JESD204 Core from the TSW54J60EVM

Yuke Tian

Part Number: TSW54J60EVM
Other Parts Discussed in Thread: ADS54J60, TI-JESD204-IP

Hello,

I am using the TSW54J60EVM and a Avnet FPGA development board for a high speed ADC data acquisition system. I set up the ADC/PLL parameters using TI's ADC54JXXEVM software. On the FPGA side, a JESD rx core is used. The test condition is: JP2 short (ADC1 has zero input). JP1 open, a 10MHz, 20mVpp sine signal was sent to J3/INBP. No input signal to J4/INBM. I am using FPGA ILA to capture the ADC data. I got the rxData from the JESD rxCore. But I am not sure how to confirm these data. My questions are:

1) What is the format of the ADC data: is it 2’s complementary ?
2) What is the ADC data frame sequence ? I.e., the ADC data order ? There are 256 bit in each from from the rxData. It looks the upper and lower 128 bits are for the two ADC channels. But I don't know the sequence within the 128bits (8 16-bit ADC data)
3) When I click the “flip ADC data” choice on the ADC setting page, I did observe that the ADC data are flipped; MSB become LSB. Does this mean the JESD204 between the TI demo board and the Xilinx FPGA board is working ? In the FPGA JESD rx Core, the rx_sync and rx_tvalid are always high.

Attached is the ILA image on FPGA, the JESD204 settings on the TSW54J60EVM and on the Vivado IP.

If anyone has suggestions, please help me on this. I have been stuck on this for a while.

Thanks a lot in advance.

-ytian

ADS54JxxEVM_FPGA_ILA_Data.pdf

over 3 years ago

0 jim s over 3 years ago

TI__Guru* 91947 points

Yuke,

The data format from the ADC can be either 2's comp or offset binary. This is set by register 0x43 bit 0 in page 0x6800. By default, this is set to 2's comp after a reset.

In regards to your other questions, see tables 11 and 13 in the ADS54J60 data sheet for how the data is sent on each ADC output lane. Please see attached document for more information on how the data is formatted using the Xilinx JESD204B IP core. You may also want to contact Xilinx regarding your questions as this is related to their product not ours. If interested, TI does offer free Xilinx FPGA JESD204 IP that includes documentation and example reference designs. Go the following to request this IP:

https://www.ti.com/tool/TI-JESD204-IP

Regards,

Jim

Xilinx JESD204B IP.pdf

0 Yuke Tian over 3 years ago in reply to jim s

Prodigy 80 points

Hello Jim,

I appreciate your response. With your help, my project is moving forward. Thanks a lot ! I have requested the TI-JESD204-IP and will give it a try once I obtain it from TI.

Meanwhile, I continued with the Xilinx JESD204 core. When I used SysRef pulse from ADS54JXX EVM GUI, I got the valid rx_Sync and rx_tvalid signals on the FPGA side. When I flip the ADC data, the rx Data in the FPGA are also flipped. I don't need to re-generate SysRef -- the rx_Sync and rx_tvalid stay solid high for long time after the first SysRef pulse train. I assume this means the data is being reliably sent from TI TSW54J60 to Xilinx FPGA. Is this correct ?

But my new puzzle is that the ADC data doesn't make sense. A 10KHz, 20mV sine waveform signal is connected to the J3 (INBP). The INBM is not connected to anything (from the schematics, it is grounded by zero ohm resistor R119). The JP2 is short so the input of channel 1 is zero. I thought the expected RX data will be around 0 for INA, and sine waveform for INB. But the two channels both show some "random" data. The ADC is set to two twos complement format. I tried to reset the ADC core and change the gain, it doesn't help. Did I miss anything on the ADC setup ? Does the ADC continue doing the conversion on every DCLK (983.04MHz) ?

Another observation: from the ADS54JXX EVM GUI, when I change the JESD test pattern to D21.5, the rx_tvalid is high and all 8 lanes data is 0x0808. Is this normal ?

Attached are four FPGA ILA screenshots. The first one is the signals when SysRef is pulsed 8 times at beginning. The second one is the zoomed ADC data after the 8 SysRef pulse train. The data's format is hex. The third one is the same as the second one, except the data format is singed integer. The fourth one is the data when constant D21.5 is used for JESD test pattern.

Thanks in advance for your suggestions.

-Yuke

Fig.1 The signals after the initial SysRef pulse train.

Fig.2 Zoomed in data (hex format) after the after the initial SysRef pulse train.

Fig.3 Zoomed in data (singed integer format) after the after the initial SysRef pulse train.

Fig.4 Data when ADC is set to constant D21.5 test pattern

0 Yuke Tian over 3 years ago in reply to Yuke Tian

Prodigy 80 points

I found the cause of the ADC random data. The PDN (power down) pin was short to ground on the board. There is a register bit (bit 6 of Analog register x26) to override this PDN pin. The default is zero and the analog section is powered down by the PDN pin. Once I set this bit to 1, I got the sine waveform from the input signal. Now this puzzle is solved.

Many thanks to Jim, Raj and others in this forum. It is a great forum.

Cheers,

Yuke

10MHz sine waveform. 100mV peak to peak, 50mV offset, Gain=2dB

5MHz sine waveform. 100mV peak to peak, 50mV offset, Gain=2dB

1MHz sine waveform. 100mV peak to peak, 50mV offset, Gain=2dB

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TSW54J60EVM: Understand the raw data format received on the FPGA JESD204 Core from the TSW54J60EVM