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ADS1118-Q1: AIN0, AIN1, AIN2, the data between the channels strikes

Part Number: ADS1118-Q1
Other Parts Discussed in Thread: ADS1118


On the hardware connection, we collect three signals, which are respectively connected to ain0, ain1 and ain2, and the signal reference ground is connected to ain3,
The acquisition mode is 001, 010 and 011 in the configuration register,
Sampling rate 128sps, FSR is ± 6.144 V ,Continuous-conversion mode ,ADC mode (default) ,NOP[1:0] =01。
In practical application, we change the configuration register config register every 10 ms and read the data of each channel,
However, it is found that the data of each channel is in series with each other.
Ain1 will display the signal input values of ain1 and ain3 at intervals, ain2 will display the signal input values of ain2 and ain1 at intervals, and ain3 will display the signal input values of ain3 and ain2 at intervals.
When the change interval of the configuration register and the sampling read interval are increased to 100ms, the phenomenon disappears, and the sampling data is stable and accurate.
What is the reason for this phenomenon? Is there any problem with software or hardware? 100ms for the actual sampling rate is too large to meet the requirements
  • Hi Neal,

    How are you determining that the data is ready to be read by the MCU? Are you polling the DRDY pin to look for a high-low transition per section 9.5.5 in the ADS1118-Q1 datasheet? Or are you just reading back data every 10 ms?

    And are you saying the data is the sum of individual channels? For example, if AIN1 = 0.5 V, AIN2 = 1.2 V, and AIN3 = 1.9 V, then

    • When you read back AIN1 you would get AIN1 + AIN3 = 0.5 + 1.9 = 2.4 V?
    • When you read back AIN2 you would get AIN1 + AIN2 = 0.5 + 1.2 = 1.7 V?
    • When you read back AIN3 you would get AIN2 + AIN3 = 1.2 + 1.9 = 3.1 V?

    Or are you reading the difference between these channels e.g. AIN1 = AIN1 - AIN3?, etc.?


  • Hi Bryan,

    According to the schematic diagram, ain3 is actually the reference ground of external signal. Its potential is equivalent to the reference ground potential of ADC, so the input voltage is 0V.
    So in theory,
    Suppose ain0 = 0.5V, ain1 = 1.8V, ain2 = 3V, ain3 = 0.01V
    However, when we read the sampling value of ADC0, we will read that the value of ADC0 jumps between 0.49v and 1.79v, showing 0.49v and 1.79v; ADC1 will jump between 1.79v and 2.99v; ADC2 will jump between 2.99v and 0.49v.
    When the change interval of the configuration register and the sampling read interval are increased to 100ms, the phenomenon disappears, and the sampling data is stable and accurate
  • Hi Neal,

    Thanks for the additional information. In my previous example I had meant to say HALL1, HALL2 and HALL3, not AIN1, AIN2 and AIN3, so that is my mistake for not being clear. Thanks for clarifying.

    I had asked in my previous email how you knew when to take data. Usually you are looking for a high-low transition on DRDY, but some engineers will just use a timer that can cause data readback errors. Can you let me know how you are reading back data from the device? You can also send me a short portion of your code that covers how you change the inputs on the ADS1118 and reading back data.


  • Hi Neal,

    Also, if you have a logic analyzer it would be helpful to see the different SPI transactions you are sending to and receiving from the ADC. This will help us understand if the data being sent to the ADC is correct, as well as the timing.