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DAC80508: design parameters confirm

FRANK1
Expert 8675 points
Part Number: DAC80508


Hi Sir,

I have some technical queries on DIV, GAIN value for DAC80508MC.

My design spec）
　16bitDAC : I use DAC80508MC.
　1) 0V output when Reset
　2) Data write ± Output 10V.

Investigation）

 For the configuration of figure 78 of the 389.2 physical application,

 I using calculation formula of 9.2.1 Design Requirements,
　When GAIN ＝ 1 ,　Vref ＝ +2.5V,
　CODE ＝ 65536, 32768, 0、
　I confirmed Vout　＝　+10V, 0V, -10V .

Question）
However, DIV value：1、GAIN value：1　is 「Not recommended」 in Table 1. DAC Output Range Configuration of page.22 9,3,1,2 Output Amplifiers


Confirmation）

　In this condition of DAC80508MC、Vref＝+2.5V、
   1) 0V output when Reset
　2) Data write ± Output 10V.
　
Q１）is the above design parameters possible?

Q２）If possible, can you tell me the DIV value and GAIN value？

dac80508.pdf

Thanks for your clarification.
Regards,

  • 0
    TI__Mastermind 19096 points

    Hi,

    The fig 78 assumes DIV by 2 and Gain  =x2. 

    GAIN = 1 in the datasheet means the bit setting, not the actual gain

    Assumption is made in such a way that DAC out is always 0 to Vref in figure 78 and converts to -10 to +10V using the op amp stage

    If you want RESET DAC output to be 0V, please use the Z device, not M ( Clarify where you need 0V, on DAC side or after the Op amp stage).

    Regards,

    AK

  • 0 in reply to Akhilesh K
    TI__Expert 8675 points

    Hi AK,

    There may be some confusion。

    I will send you a question about DAC80508MC again.

    I use manual of Dac80508.pdf.

    Please find the questions in figure 59.

    1) default value

    Is DIV ＝ 1、GAIN ＝ 2 correct?

    2) is the DAC output = 1.25V correct when the clear signal is input?

    3) if a clear signal is input, please tell us the value of the DAC active register.

    Thanks.

  • +1 in reply to FRANK1
    TI__Mastermind 19096 points

    Hi,

    For M device, Gain  = 2 and Reference divider = 1 by defualt. REF_DIV bit is set to 0 for both M and Z devices

    With 2.5V internal reference, full scale ouput is 0 to 2*Vref (by default), so for M device expecttion is after power on reset value should be 2.5V

    With CLR input, you are going to clear the DAC_DATA regsiters and buffers, not the configuration register.

    So after POR, if you apply CLR input, output should be 2.5V for M device and 0V for Z device.

    DAC_ACTIVE regsiter after POR and CLR is 32768 ( 0x8000) for M devcie.

    Hope this clarifies your query. Let me know if you need more help.

    Regards,

    AK