DAC39J82EVM: Support for Xilinx Zynq Ultrascale plus EVM ZCU106

Kiran,

The ZCU106 did not route the SYNC traces that are used by the DAC EVM. To get this interface to work, you would have to jumper the SYNC signal from the ZCU106 by using a spare signal from the FPGA that may be routed to a connecter (if there is one)y, then send this to J21 of the DAC EVM. The FPGA would have to provide a 1.8V CMOS level signal for this to work. For some reason, Xilinx forgot to route this critical signal on all Zynq platforms. Per the JESD204B standard, this is FMC pins F10/F11.

Regards,

Jim 

Hi Jim,

Thanks for the quick response and the details provided.

Currently, we feel this could be one of the possibilities: ZCU106 has 2 PMOD connectors (J55/J87) both of LVCMOS18 IO standard. A wire/some connection must be made between the ZCU106's J55/J87 pins and DAC EVM's J21 (and of course with the Grounds).

For example, if we are using only one JESD link, then on ZCU106, connect PMOD J55.1 pin to DAC EVM's J21.1

This should work, right? Do you see any issues here? Are there any other additional settings we have to take care of in the FPGA (JESD Core) or at DAC when we use Sync in LVCMOS mode?

I agree, It's very unfortunate that Xilinx doesn't connect these FMC signals on all Zynq EVM platforms, because the same signals are connected in other EVMs (like KC705)

Thanks,

Kiran