This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS8588S: reading data error through spi interface

Part Number: ADS8588S

Hello,

I have a problem reading the ADC data from spi interface of the ADS8588S.  In the board there are two different ADCs and both behaves in the same way. the ADC are commanded by an FPGA, below an image of the waveforms taken from the Integrated Logic Analyzer of the Zynq device.

/resized-image/__size/320x240/__key/communityserver-discussions-components-files/73/FRSTDATA_5F00_issue.png

After the busy signal goes low, the spi communicatin starts. the CS (nADC1SPICs signal) goes low and the data are read back using both DOUTA and DOUTB (ADC1SPIMisoA_1 and DC1SPIMisoB_1 signals). 16x4 clock cycles are provided before the CS signal is deactivated. during the spi communication, a strange behaviour appears on FRSTData signal: 

instead of remaining high for the first 16 colck cycles, the FRSTData signal goes low after two clock cycles and then a pulse every 8 clock cycles is present until the end of communciation. moreover, on DOUTA and DOUTB there is the same waveform that is not related to the voltage level at the input of the ADC.

anyone else has experienced the same problem? do you have an idea of the root cause of the problem?

  • Hi Fabio,

    FRSTData should be only active high for the data from the first channel, like Figure 70 in the ADS8588S datasheet. Are you conversion code correct for all channels? Do you share a same SPI interface for both ADCs? 

    I will see if I can check the timing on the EVM. I will let you know soon.

    Best regards,

    Dale

  • Hi Dale,

    I have two separated and independent SPI for the two ADC, each one with its signals (CS, clock, DOUTA and DOUTB).

    both ADCs behave in the same way. below some pictures taken from the second ADC:

    CH1 (yellow): CS

    CH2 (blue): FRSTDATA

    CH3 (red) & CH4 (green): DOUTA & DOUTB

    --------------------

    CH1 (yellow): CS

    CH2 (blue): spi clock

    CH3 (red): Busy

    -------------------------------------

    as you can see, also in the second ADC, the FRSTDATA signal seems not in line with figure 70 you mentioned above. moreover, the conversion code acquired on DOUTA and DOUTB is the same (i.e. CH1=CH5; CH2=CH6=CH3=CH7=CH4=CH8) and it seems completly random. my opinion is that the behaviour of the FRSTDATA impacts also on the data the ADC is providing on DOUTA and DOUTB and the result is that they are not meaningful.  

    according to your experience, is there any event that could trigger this behaviour? is it possible that the SPI interface of the ADC is in an unknown state after the reset and behaves in such a way?

    thank you for the support

    Fabio

  • Hi Fabio,

    I checked on the EVM with a special system which allowed me to implement different timings. I was able to reproduce the the timing you showed above. However, I was able to get correct data on both SDOA and SDOB and also got the correct behavior on FRSTDATA once the CONVSTA/B signal was sent to the ADC to initiate a conversion. Please see the timing comparison below:

    1. Incorrect behavior on FRSTDATA and SDOA/B without CONVSTA/B siganl:

    2. Correct behavior on FRSTDATA and SDOA/B with CONVSTA/B signal:

    Let me know if you have any other questions about ADS8588S. Thanks.

    Best regards,

    Dale

  • Dear Dale,

    thank you for your support. we solved the problem reworking the board. probably some workmanship error in the CONVSTA/B signals area of the board caused the problem

    Fabio