Hello,
I have a problem reading the ADC data from spi interface of the ADS8588S. In the board there are two different ADCs and both behaves in the same way. the ADC are commanded by an FPGA, below an image of the waveforms taken from the Integrated Logic Analyzer of the Zynq device.
After the busy signal goes low, the spi communicatin starts. the CS (nADC1SPICs signal) goes low and the data are read back using both DOUTA and DOUTB (ADC1SPIMisoA_1 and DC1SPIMisoB_1 signals). 16x4 clock cycles are provided before the CS signal is deactivated. during the spi communication, a strange behaviour appears on FRSTData signal:
instead of remaining high for the first 16 colck cycles, the FRSTData signal goes low after two clock cycles and then a pulse every 8 clock cycles is present until the end of communciation. moreover, on DOUTA and DOUTB there is the same waveform that is not related to the voltage level at the input of the ADC.
anyone else has experienced the same problem? do you have an idea of the root cause of the problem?