ADC12DJ3200: Texas ADC EVM ADC12DJ3200 with PolarFire 300 EVM interconnecion. Ramp test ok but sine wave lanes misaligned. JMODE7

Valerio Tocca

Part Number: ADC12DJ3200

Dear all,

we have a problem aligning the lanes in JESD204B IF. We use JMODE7 in the ADC12DJ3200 EVM with 8 lanes (2 channels, 8 bit per ch). When we run the ramp test, we see the lanes aligned but not in the operative mode, when sampling an analogue sine wave. We use K=32 and we interface with the Microsemi JESD RX Macro running in the PolarFire EVM connected by FMC connector. We use direct external clocking at 1440 MHz (SysRef = 2.8125 MHz).

Any clue ? Thank you very much,

Valerio

over 2 years ago

0 Neeraj Gill over 2 years ago

TI__Mastermind 20541 points

Hi Valerio,

Can you please send the screen shot of ramp test mode vs Sine wave input mode. Also how are you feeding a sine wave signal into the two channel of the ADC? Are you splitting a signal feeding into the ADC with length matched cables. is the phase between the sine wave always the same?

Regards,

Neeraj

0 Valerio Tocca over 2 years ago in reply to Neeraj Gill

Prodigy 10 points

Hi Neeraj, thank you for your reply.

We send a sine wave in single ended through VinA, the other channel is tapped so it is just noise. So we don't use matched length cables as we are in single ended. Channel A is feeded with sine wave @100KHz whereas Channel B is tapped. Acquisition after acquisition the phase between lanes seems to change and it is not always the same.

We feed the board by using just one clock @1440 MHz entering LMK_ClkIn (J22) and we use the LMK in distributor mode generating the 2.81 MHz (SysRef) and 1440 MHz for ADC (1440/512) and a 90 MHz (1440/16) + 2.81 MHz (1440/512) for FPGA.

In my next message I will include the screenshots, Thank you very much,

Valerio