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ADC3660: Synchronization of multiple ADCs in SDR output mode

Part Number: ADC3660


Is the SYNC pin on the ADC3660 designed so it can be toggled every 64 clock cycles and not cause discontinuities or muting of the signal? I am not sure how I should interpret this
line in the datasheet. I tried the sync via SPI using the EVM and while active, it looks like the NCO stops or it sitting at 0Hz until the sync is disabled.

"When trying to resynchronize during operation, the SYNC toggle should occur at 64*K clock cycles, where K is an integer. This ensures phase continuity of the clock divider."

In our application we are using 8 of these dual ADCs and plan to issue a SYNC on the PIN every time the frequency is changed. One of our applications might use the 2x DCLK (SDR) mode.
Does that change the synchronization behavior in any way?



  • Hi Pieter,

    Yes, there will be a short transition/discontinuity in the NCO output as it changes to its new frequency. If holding the SYNC pin (or register) in a "high" state, the NCO will not be present. The main idea is to provide a pulse to quickly update the NCO output.

    I've done some testing on the ADC3660EVM and TSW1400EVM that will hopefully sheds some light on use of the Sync functionality, and how fast it will take to change NCO frequencies. I've used a one-shot pulse to ensure the NCO gets updated one time, and is not held in a reset/null state.

    ADC3660 Sync Test.pptx

    In regard to the 64*K factor, this is mentioned to ensure that the NCO phase remains the same when performing an "active" (not initial configuration) NCO update. If not synchronized within 64*K, there will be an absolute phase shift of all of the mulitple ADCs (even though all ADCs will share the same phase) as compared to the previous NCO phase.

    The 2x DCLK mode will not impact the SYNC functionality.

    Best Regards,


  • Dan,

    Thanks. That answers my questions.