Is the SYNC pin on the ADC3660 designed so it can be toggled every 64 clock cycles and not cause discontinuities or muting of the signal? I am not sure how I should interpret this
line in the datasheet. I tried the sync via SPI using the EVM and while active, it looks like the NCO stops or it sitting at 0Hz until the sync is disabled.
"When trying to resynchronize during operation, the SYNC toggle should occur at 64*K clock cycles, where K is an integer. This ensures phase continuity of the clock divider."
In our application we are using 8 of these dual ADCs and plan to issue a SYNC on the PIN every time the frequency is changed. One of our applications might use the 2x DCLK (SDR) mode.
Does that change the synchronization behavior in any way?