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ADS1212: /DRDY remains high

Part Number: ADS1212


My customer need assistance.

Wiring as follows: AinP connected to analog voltage input; AinN to grounding; AGnd is connected to analog ground; Vbias is floating; CS connected to MCU; DSYNC connected to + 5V; Xin input 2MHz active crystal oscillator signal; Xout is floating; DGND to digital grounding; DVDD is connected to + 5V; SCLK\ SDIO\ SDOUT\ DRDY are connected to MCU; MODE to analog ground; AVDD connected to + 5V; REFin and REFout are grounded through capacitors.

According to the datasheet, if the voltage rising rate at 50V / s, ADS1212 will be automatically initialized. I failed, DRDY remained high. And I used the method recommended from datasheet, to input special SCLK signal. But I failed, DRDY remained high). The SCLK pulse time was 512txin < T1 < 800txin; 10txin < t2; 1024txin < t3 < 1800txin; 2048txin < t4 < 2400txin. I set the time as: T1 = 350us; t2 = 20us; t3 = 700us; T4 = 1100us (ADS1212 crystal oscillator 2MHz); No data was written to the CMR register (For DRDY never low).

Please help. Thanks.

  • Hi Chong Yu,

    I don't see anything wrong with the connections, and the timing appears to be acceptable for the RESET SCLK timing.  Both AVDD and DVDD supplies must be at the nominal operating voltage and DSYNC pulled high.  I would suggest verifying that these voltages are present at the device pins.  With an oscilloscope I would also suggest verifying that the oscillator at the device pin is also working at the expected frequency.  If the supplies and clocks are as expected, then monitor the DRDY pin with an oscilloscope.  You should see the DRDY pin toggling.

    I would also suggest that the RESET sequence be verified with an oscilloscope or logic analyzer.  Any scope plots you can send me would also be helpful to help in troubleshooting.  Is this a prototyping solution on a breadboard?  If so, can I also see some photos of the setup?

    Best regards,

    Bob B