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ADS131M08: ADS131M08

Part Number: ADS131M08


 We have built 1st prototype of our new design, based on ads131m08, 8 chan 24bit ADC.

We are using the internal 1.2V vref, with OSR=16384, Clk in = 2MHz

 Topic 1

After performing some tests, I would like to get more info regarding calibration process, data sheet section 8.3.11

There are the following registers for each channel: OCALn[23:0] and GCALn[23:0]

Do you have an app note, with exact procedures, step by step, on how to perform calibration process?


Topic 2 

Using data sheet section 8.3.2  Input Multiplexer, we are setting ALL channels to MUX0[1:0] to MUX7[1:0] = 10 --> inserting the positive test signal to all channel.

We are using internal reference voltage of 1.2V, all calibration registers are at default values.

Measured results:



















Per data sheet we should get exact 160mV…

Chan1 is the closest to this value, but the remain have large error

Can you share more info on that? Are we doing something wrong?

This is also related to calibration process



  • Hello Eran,

    Welcome to our forum and thank you for your post.

    To better understand how gain and offset calibration are performed, I recommend reviewing this training video on our TI Training Portal:

    The results you shared from your positive DC test signal measurements seem very reasonable. It is not expected to measure exactly 160 mV due to a multitude of error sources, such as thermal noise, offset and gain error, internal resistor divider tolerance, and reference voltage accuracy. 



  • Hi Ryan,

    Thank you for your prompt reply.

    To be more specific with our  ADS131M08, and the measured positive Test signal, there is too much different between the input channels, but it is what it is. Please note that this type of result was measured on more than one units.

    Moving forward, regarding calibration, our design don't support built in test calibration of 2 points nor GND for any of the 8 channels inputs, and therefore, I was thinking of using the internal Test signals, and MUXn ADC feature for ADC IC calibration level only:

    Point 1: MUX0[1:0] to MUX7[1:0] = 10 --> inserting the positive test

    Point 2: MUX0[1:0]d to MUX7[1:0] = 01 -->Short to the Analog ground

    From all the noise factors mentioned above, the resistor divider is the factor that isn't used in the "real" application, and this is my concern regarding this calibration effectiveness.

    VREF data sheet mention 1.2V with +/-0.1% error, and according to chan1, it seems that VREF is OK, leaving me with other factors...

    Do you recommend this IC level calibration? I assume the internal test signals purpose are for this reason



  • Hi Eran,

    The internal test signals are provided primarily for debugging purposes to validate device configuration and SPI communication. The positive and negative DC test signal voltages are not trimmed accurately enough to use for true calibration. 

    The MUX[1:0] = 01b setting will internally set both ADC inputs to ground. This allows for an accurate measurement of the ADC channel noise and offset voltage with a 0-V differential input. We tie the inputs to ground during this test so that the common-mode is not left floating. I do recommend this test and storing the IC offset calibration value for each channel in the CHn_OCAL_MSB and CHn_OCAL_LSB registers.



  • Hi Ryan,

    Thank you!

    we shall perform just the offset calibration