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DAC3174: bandwidth and latency

SM
Expert 1730 points
Part Number: DAC3174

Hello,

    We are planning to use the DAC to generate I and Q and feed them to a analog IQ modulator. A few questions here:
1) What is the maximum bandwidth of the analog signal that can be generated with such an approach. Is it 500MHz (since I and Q)? 

2) Are there any issues with this approach to generate pulsed signals? 

3) How to design the interface circuitry? The IQ mixer used is a passive mixer. 

4) We plan to generate I and Q centered at 0Hz, sampled in the FPGA at 500MHz (since the DAC is also operating at 500MHz). What is the maximum bandwidth of the signal that can be generated?

5) What is the latency of the device. (digital data input to analog output). Section 6.6 of datasheet mentions this as 26 DAC clk cycles, does this mean 26 x 2ns (500MHz) = 52ns? 

Thank you for your help in advance,

  • 0
    TI__Mastermind 18195 points

    Hi SM,

    1. You are correct, 500MHz would be the max bandwidth
    2. There shouldn't be any issues regarding pattern supplied to the DAC at all.
    3. The interface itself will not be vastly different than if using an active mixer part. I would suggest following the DAC3174EVM schematics as a reference for this. Alternatively, you can find TI reference designs for IQ mixers at this link.
    4. This should stay at 500MHz since the DAC is a DDR (dual data rate, interleaved with channel A on rising edge of clk, channel B on falling edge of clk)
    5. Correct, (26 'CLK') * (1/Fs 'seconds/CLK'), @ 500MSPS -> 52ns of digital latency.

    Thanks