Hi team,
I'd like to know the output data timing.
If there are input signals on ch1 and ch2 at the same time, which channel is converted?
Is there a priority?
Sincerely.
Kengo.
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Hi Kengo-san,
Thanks for the post.
There is no priority as to which channel is converted. Each DDC112 input has two integrators (Integrator 1A/1B and Integrator 2A/2B) which will continuously integrate the input channels based on the CONV signal. With the DDC112 in continuous integration mode, the output of the integrators from one side of both of the inputs will be digitized while the other two integrators are in the integration mode. Please refer to Figure 2 of the datasheet for the integration and conversion timing for the DDC112 in continuous mode. The results from side A and side B of each signal input are stored in the output shift register and are valid when the DVALID output goes low.
Thanks
-TC
Hi Kengo-san,
Please see the diagram (Figure 22) below for the data output scheme of the DDC112. Both IN1 and IN2 output data need to be serially retrieved from the DOUT with IN2 output data bit followed by the IN1 output data bit. There is no option to specify only a specific channel for retrieval.
Thanks
-TC
Hi Kengo-san,
The falling edge of /DXMIT in combination with the DCLK will initiate the serial transmission of the data. IN2 channel data will be output first, followed by the IN1 channel data.Thanks
-TC
Hi Kengo-san,
Sorry, can you clarify the question as I am not clear as to what the question is?
Thanks
-TC
Hi Kengo-san,
Thanks for the clarification. Unfortunately, there is no option to retrieve the data with the scheme you have shown.
Thanks
-TC
Hi TC-san,
Thank you for your comment.
Unfortunately, my customer saw a phenomenon that CH1 and CH2 were reversed.
I attached the waveform.
210802_DDC112U_Waveform.pdf
This phenomenon rarely occurs.
It recovers when the power is restarted, but when it happens, the channel is output in reverse.
Sincerely.
Kengo.
Hi Kengo-san,
Sorry, I miss your previous post.
I am not sure how this is possible that the output data is reversed. I will check with the team and see if there is an explanation for this phenomenon.
Can you provide more information regarding the device operating conditions (Cont/Ncont Mode)? It would be helpful if you can show the CONV and DVALID signals on the scope plots. In addition, please show the Side A and Side B data on the same scope capture plot for both the normal and abnormal cases.
Thanks
-TC
Hi Kengo-san,
Thanks for the patience. I have talked to the team, and the phenomena they are seeing may be due to how the CONV signal behaves during power-up conditions. Please refer to the E2E post below for more information and recommendations.
Thanks
-TC
Hi Kengo-san,
All the unused digital and analog input pins must be LOW prior to device power-up sequence .
Thanks
-TC
Hi TC-san,
I have some additional questions.
1. On power-up sequence, should the VREFpin Low?
2. Is it OK below the circuit?
I think it can not be fixed Low when power-up sequence.
3. Could you tell me about the input timing of CLK after power-up?
Sincerely.
Kengo.
Hi Kengo-san,
1/2. At the time of power-up, the VREF can be biased to a voltage other than 0V; however, it should never exceed AVDD.
3. We do not have specific timing for CLK after power-up. After the power supplies are stabilized, the system CLK can be applied to the device.
Thanks
-TC