question about ADS1252 CLK pin

Actually, I have some thoughts about what needs to be done. Can someone comment if either of these is the best solution:

1) Use an external oscillator (as opposed to a crystal), which has an output that can be connected to the CLK pin of the ADS1252.

2) Connect CLKO of microcontroller (e.g., in our project's case, the Atmega328 chip) to the CLK pin of the ADS1252.

Bob, thank you.

Any specific part/link, TI or otherwise, you can recommend for purchasing the external oscillator?

Searching for clock oscillator seems to give me mostly the 2-pin crystal kind unfortunately...

I think for initial prototyping, I will order units from the S33xx series (quite low jitter), the DIP version of C33xx. Thank you Tony.

On a different note, I have a question regarding the sequence of operations for the ADS1252 (datasheet here: http://focus.ti.com/lit/ds/symlink/ads1252.pdf).

(Given that it's the same ADC model, I don't know if I should create a new thread for this, therefore, I continue the discussion here.)

Actually, this is more of a pseudocode I've written for myself, which I'm hoping could be useful to others as well.

Could you please comment on the correctness of this generic sequence of operations to be used for ADS1252? Feel free to make any additional suggestions.

Note, my pseudocode is based on TI's application note, which gives an example of ADS1252 interfacing. See http://focus.ti.com/lit/an/slaa242/slaa242.pdf

Pseudocode

A general summary of what I'm doing:

The ADS1252 has DRDY (converted data ready indication) and DOUT (actual data output) both on the same pin, one followed by the other in a chronologically structured way, so one can use proper timing and interrupts to check when data is ready and when to get data.

So my plan, based on the method described in the application note, is to initially have the microcontroller reset the ADC, so that we have awareness/control of the timing from then on. The DRDY phase lasts for 36 MCLKs (modulator cycle periods), and the DOUT phase lasts for 348 MCLKs. At the end of each conversion cycle (36 + 348 = 384 MCLKs total), there is a low-to-high (RISING edge) in the transition from the end of DOUT to the beginning of DRDY.

MY INITIAL SEQUENCE

1)
ACTION: reset by holding SCLK high for at least 4 conversion cycles
(1 conversion cycle = 1 DRDY + 1 DOUT = 36 MCLK + 348 MCLK = 384 MCLK)
result: ADC is held into reset

2)
ACTION: write SCLK LOW after holding it HIGH for 4 conversion cycles
result: ADC is released from reset and begins operation

Then, for each of the conversion cycles, I do the following in a loop...

LOOP begin

1)
time_position: 0th MCLK; Beginning of conversion cycle, i.e., beginning of DRDY partition
ACTION: delay for an amount of time equivalent to 36 MCLK cycles
result: remaining time (36 MCLK cycles) of DRDY partition simply passes

2)
time_position: 37th MCLK; End of DRDY; Beginning of DOUT partition
ACTION: read 24 bits of data
result: data read into microcontroller memory
(note: due to filter, data only starting from the 6th conversion cycle after reset is valid; see datasheet for details regarding the digital filter)

3)
time_position: nth MCLK (post data-read-time); Somewhere in the middle of DOUT partition
ACTION: wait until interrupt triggered on DOUT/DRDY-line going from LOW to HIGH (i.e., RISING)
result: remaining time (post data-read-time) of DOUT partition simply passes

LOOP end

_____________

Cheers,

Gamin

Hi Gamin,

Your psuedocode looks like you are on the right track. The only thing I could not tell is if you are using the /DRDY as an interrupt to signal wait t3 required time and then send SCLKs. I would recommend using the /DRDY as an interrupt rather than just try and time out when new data is going to be ready. Keep in mind, a lot of the timings regarding Dout/DRDY are typical values so it is not necessarily true that, for example t3, is going to be exactly 6*CLK.

Regards,

Tony