ADS54J42: ADS54J42 SNR performance degradation

Hi JH,

Is it possible for the customer to use a sinewave input signal and send us an FFT plot? This looks like a modulated signal.

Also, could you please send over the sampling rate used and a list of the spi registers used as well to configure the ADC?

This will help resolve the issue.

Thanks,

Rob

Hello Rob,

Thanks for your help.

Please see additional information below.

Fs = 491.52MHz

WR,0x0000,0x81

WR,0x0011,0x80
WR,0x0039,0xC0
WR,0x003A,0x40
WR,0x0056,0x04
WR,0x004F,0x01
WR,0x0059,0x20

WR,0x4004,0x68
WR,0x4003,0x00
WR,0x60f7,0x01
WR,0x604E,0x80
WR,0x6042,0x01
WR,0x6000,0x01
WR,0x6000,0x00

WR,0x4004,0x6A
WR,0x4003,0x00
WR,0x6016,0x02
WR,0x6017,0x40
WR,0x6017,0x00

WR,0x4004,0x69
WR,0x4003,0x00
WR,0x6001,0x04
WR,0x6000,0x80
WR,0x6006,0x1F

Thank you.

JH

Hi JH,

This FFT plot makes more sense, first, we typically look at the real portion and throw away the imaginary part of the FFT.

If you look closer around the fundamental frequency, the issue is the clock phase noise is too high. Therefore, this will lower the SNR performance.

Can you tell me a little about the clocking signal chain they are using, or if they are using a signal generator/test equipment for the clock?

Thanks,

Rob

Hi Rob,

The customer used the LMK04806 as the ADC clock generator.

They checked the clock phase noise performance as shown below.

1) 30.72MHz VCXO phase noise

2) LMK output - 491.52MHz phase noise

Could the above clock phase noise performance be the cause of the poor ADC SNR performance?

Regards,

JH

Hi JH,

Yes, that could be very possible. Would it be possible for the customer to share the schematics of the design?

Regards,

Rob

Hi Rob,

The below is the ADC & Clock schematic. Please review if there are any problems.

The figure below is the ADC output FFT plot with and without input signal.

When there is an input signal, the noise floor rises by about 15dB overall.

Is it correct that this is due to the degradation of the clock's phase noise performance?

Thanks a lot.

JH

Hi Rob,

The customer tried to improve the phase noise of the clock as shown below, but there was no change in the ADC SNR performance.

Please review whether there are other causes that cause ADC SNR performance degradation.

Thank you.

JH

Hi JH, 

It is possible the noise is coming from both and clock and analog input.

I saw the schematic but this doesn't give me enough detail.

Can you ask the customer to give me the full schematic of the clock signal chain and also the a block diagram of the test measurement setup?

This would greatly help. If they are using signal generators for either the clock and/or analog input. Please note that on the block diagram test setup.

Regards,

Rob

Hi Rob,

Could you please email me (jh.shin@arrow.com) with the detailed information you need from the schematic?

The customer has already shared the ADC and clock schematic.

Regards,

JH

Hi JH,

Yes, I will email you. The posted schematics are difficult to read for details.

Thanks,

Rob