This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC32RF45: DDC Ramp Test Pattern - how to enable?

Part Number: ADC32RF45

What register writes do I have to perform to enable the test pattern generator within the DDC (Figure 111 in datasheet)?  I normally have the DDC disabled in my design.  I added the following two writes to my initialization script just after the JESD interface setup:

0x5000 0x01 (Enable Decimation Filter)

0x5037 0x04 (Digital Ramp Test Pattern)

The addition of these two lines caused my JESD interface to not come up.

I have used the JESD204B Link Layer test pattern quite a bit with no issues.  I'm trying to use the DDC test pattern to see if there is a deterministic trend between the test pattern values and the jesd "start of multiframe" after power-up and initialization.


  • Hi Shawn,

    You can install the ADC32RF45EVM GUI to check register writes under the "Software Development" tab here:  

    The writes to 0x5000 and 0x5037 are correct to enable the DDC and a digital ramp test pattern. However, a write to set the decimation factor (0x5001) is also needed (see table 28 in the ADC32RF45 data sheet for reference). The decimation factor will also change the SERDES rate, so you will need to adjust the clock speed accordingly.

    Once the GUI is installed, you can select your desired parameters in “Quick Setup”, including the decimation factor in the DDC. Under the “ADC32RFxx” tab, you can set the Ramp test pattern. Then you can select “Program EVM” and double right click on the bottom left corner to view the status log of register writes: