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ADC32RF45: Sub-ADC sample placement within JESD data

Part Number: ADC32RF45

I am operating my device in LMFS=82820 mode and JESD data arrives exactly as seen in Table 15 of the spec.  Does properly functioning deterministic latency guarantee that samples from each of the four sub-ADCs (I don't know the correct terminology here) always align the same way within the JESD frames after each power-up?

On my hardware I believe that this is not the case because I have a spur correction algorithm that requires me to shift coefficients (or samples) after each power cycle.  The coefficients are initially created assuming the sub-ADC alignment is always the same.