• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 45 subscribers
  • Views 218 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1232: System design: Does shifting Vref to re-range load cells work?

Dave McMahan
Prodigy 110 points
Part Number: ADS1232

I am using the ADS1232 but I think this might be a more general question regarding load cell design.

Almost all designs I see will tie Vref to the analog voltage rails.  This gives a max range of +/-19.5 mV with maximum gain on the ADS1232.

My load cells will give more like 5 or 6 mV (total swing) over the range I expect to use.  The load cell is rated at 37.5 lbs, I only need to go up to 20 lbs.  I have a 39mV range to cover a ~7 mV swing.  I would think it is rare for a load cell to cover close to the perfect 19.5 mV max value without some kind of analog tinkering to scale things properly.

I would think it should be possible to design a voltage divider for Vref that narrows down the ADC range to span just what I need (plus appropriate margin, of course).  A simple voltage divider with three series resistors across the excitation voltage should work, with Vref+ and Vref- connected across the center resistor.  In this case, I need my Vref to span about -0.5mV to 6.5 mV, so the ADC result will go from almost the minimum count value to almost the maximum count value over the desired range.   This change would give me around two more bits of usable resolution for the price of three resistors.

Likewise, my scale has a dynamic range of 20 pounds, but I expect the pan will weigh something like 6 pounds.  If I was really smart I would bias Vref so the scale to covers a range of 6 to 26 pounds on the load cell, because I don't need to count the pan in my dynamic range.  The total of load+pan weight must still be under the 37.5 lb limit of the load cell, but that's not a problem here.

Is this a valid way of thinking?   I know there are limits as to how narrow the Vref span should be, but 5 volts all the time seems to ignore the fact that scales don't report negative values.  Nothing weighs below 0 pounds.  I don't need the full negative range, so why not repurpose it into a usable area and normalize it all  with calibration and tare?   I don't recall seeing anybody mention doing this to properly match load cells ranges to the ADC range.

  • +1
    TI__Guru** 112795 points

    Hi Dave,

    I think a lot of what becomes confusing here is expectations relative to desired measurement range and repeatability.  You could use a voltage divider for the reference to improve the dynamic range, but that does not translated directly to increased accuracy or repeatability.

    When you add a resistor divider (and by the way the minimum reference input voltage is 1.5V for the ADS1232) you need to also take into account any inaccuracies of the resistor divider as well as any thermal drift of the resistors.  You will also add some thermal noise from the resistors as well.  This combination will add error to the measurement both in terms of additional noise and gain error.

    Next consideration is you cannot overcome the inherent noise of the PGA and oversampling modulator.  So just increasing dynamic range will not necessarily increase the ability to resolve to a smaller value.

    Another consideration is the ADC is what it is designed to be.  The ADS1232 was designed as a differential input ADC.  That is AINP relative to AINN and the conversion result is in binary 2's complement.  There is no unipolar output code option for this device.  In your case a unipolar output format would be desirable, but not all load cells report output in a single direction.  The measurement of strain can be measured in both directions depending on the load cell design.  So there are some limiting factors when using the ADS1232 in your design.

    Let's return back to repeatability.  Sometimes this is called flicker-free resolution.  From the perspective of the ADC it is called noise-free resolution and can be considered in bits or uV (or nV when gain is applied).  From the ADS1232 datasheet noise tables we see that the lowest noise is by using 5V AVDD and 10sps data output rate.  Using the maximum available gain the peak-to-peak noise (or noise-free) is 110nV.  So this is the best the ADC can do regardless of reference voltage.  Also shown in the table is the number of noise-free bits as 18.4 when using a 5V reference.

    When you lower the reference voltage you will also lower the noise-free bits.  The reason is the ADC noise remains the same.  The resolution size per bit is smaller appearing to utilize more of the full-scale range, but the noise cannot be overcome.  If the full-scale range (FSR) is +/- 6.5mV (or 13mV total), then the noise-free bit resolution is 16.85 because the noise is still 110nV.

    So it is not the reference voltage that is the limiting factor but the inherent noise of the ADC.  The repeatability with respect to the noise is weight / FS output * noise.  In the scenario provided 20lbs / 6mV * 110nV = 0.000367 lbs.  In the end this results to about 54000 counts regardless of the reference voltage.  I can tell you that the noise and drift will be worse if a voltage divider is used.

    So the recommended ratiometric measurement using the same voltage for the excitation and reference will provide good results and removes some of the issues with increased complexity, error and drift as compared to the voltage divider circuit.  Note that this is all theoretical and does not take into account any additional noise from external sources picked up in wiring, etc.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 110 points

    >  So the recommended ratiometric measurement using the same voltage for the excitation and reference will provide good results and removes some of the issues with increased complexity, error and drift as compared to the voltage divider circuit. 

    Nice write-up.  It sounds like there is potential for some gain but nothing like what I was hoping for.  I figured there was no real way to cheat the universe, or TI would have written an app note for that.