Hello,
I am using ADS62P25IRGCT in my design
The Input to CLKP and CLKM (Pin no: 25,26) is from FPGA
The FPGA is working in 1.8V supply
AVDD and DRVDD of the ADC is connected to 3.3V
will it be an issue if I provide the clock from FPGA to CLKP and CLKN
And also connect the CLKOUTP and CLKOUTM back to the FPGA itself
will these voltage levels will be a problem
The FPGA can drive as LVDS with a common-mode voltage of 1.2V
Regards,
Tensil Sebastian
