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DAC80502: VREFIO shows 2.5V with REF5050

Part Number: DAC80502
Other Parts Discussed in Thread: REF5050,

Dear Technical Support Team,

I use DAC80502 with REF5050.

Expected output voltage of REF5050 is 5V, however it shows 2.5V.

I tried to change external reference mode (disable internal reference: Address:0x30 data 0x0100).

However it doesn't change 5V reference correctly

Input voltage of REF5050 is 10V and I can see it with oscilloscope.

How do I improve 5V output. See attached schematic.

DAC80502+REF5050.pptx

Can I read the register value with SPI mode?

Now I tried to write register such as Fullscale(Reg 0x08 , 0xFF ) , however output doesn't change from 0V to 5V.

Best Regards,

 ttd

  • Hi ,

    Welcome to e2e.. i can support your query.

    The observation on VREFIO = 2.5 is expected, REF-DIV = 0(by default) and  REF-DIV bit need to be set "1" to get 5V.

    refer reference input condition in datasheets under 7.3 section. 

    To enable REF-DIV = 1, write reg (0x04, 0x100).

    Hope this will solve your problem.

  • Hi ttd,

    1. When using a 5V VDD and 5V reference, the REF-DIV bit should be set to 1, and the BUF-X-GAIN bits should be set to 1 to get the full 5V output scale.
    2. You can only write in SPI mode. Read is not available because there is no SDO pin on this device. You can read and write in I2C mode. 

    Best,

    Katlynne Jones

  • Hi Katlynne Jones,

    Thank you for your reply.

    1. 37 page shows steps, however I can’t get correct output.

    The following text shows the pseudocode to get started with the DACx0502:

    //SPI Settings

    //Mode: Mode-1 (CPOL: 0, CPHA: 1)

    //CS Type: Active Low, Per Packet

    //Frame length: 24

    //SYNTAX: <WRITE REGISTER (HEX ADDRESS)>, <HEX DATA>

    //Disable internal reference (only in case of external reference)

    WRITE CONFIG (0x03), 0x0100

    //Select REFDIV=1 (reference divided by 2) and GAIN=1 (gain at both the DAC outputs is 2)

    WRITE GAIN (0x04), 0x0103

    //Write mid-code to DACA

    WRITE DAC-A (0x08), 0x7FFF

    //Write Full-code to DACB

    WRITE DAC-B (0x09), 0xFFFF

    2. 
    8.5.1.1 SPI MODE

    This shows SPI format and bit 23 is R/W.

    Should be always low for write access?

    Best regards,

    ttd

     

  • Hi ttd,

    You said "Expected output voltage of REF5050 is 5V, however it shows 2.5V." Where were you measuring this 2.5V? At the VREFIO pin of the DAC? Or the DAC outputs? I think I misunderstood earlier.

    Yes, the R/W bit should always be held low for write. If this device had an SDO pin, the R/W bit would be brought high during read cycles. 

    Do you know if you have been able to write to the DAC? If you were seeing the 2.5V on the VREFIO pin, then I am guessing your SPI command to disable the external reference wasn't successful. Can you measure the SPI signals (ideally SYNC, SCLK, and SDA together) using an oscilloscope and send us a screenshot? We can take a look and possibly find what's going wrong with your SPI communication. 

    Best,

    Katlynne Jones

  • Hi Katlynne Jones,

    Thank you for your quick reply.

    >You said "Expected output voltage of REF5050 is 5V, however it shows 2.5V." Where were you measuring this 2.5V? At the VREFIO pin of the >DAC? Or the DAC outputs? I think I misunderstood earlier.

    ⇒I see 2.5V on VREFIO. I guess that internal reference isn't disable(external reference isn't enable) on REG 0x03 ,0x0100 through SPI. 

    >Yes, the R/W bit should always be held low for write. If this device had an SDO pin, the R/W bit would be brought high during read cycles. 

    ⇒OK!

    >Do you know if you have been able to write to the DAC? If you were seeing the 2.5V on the VREFIO pin, then I am guessing your SPI >command to disable the external reference wasn't successful. Can you measure the SPI signals (ideally SYNC, SCLK, and SDA together) >using an oscilloscope and send us a screenshot? We can take a look and possibly find what's going wrong with your SPI communication. 

    ⇒I'll try to get waveform with SYNC, SCLK, and SDA together and update to you.

    Best Regards,

    ttd

  • Hi Katlynne Jones,

    I can get correct DAC output and VREFIO=5V.

    I checked SPI signals (SYNC, SCLK, and SDA together), then SYNC assert timing isn't correct.

    I fixed SYNC timing.

    Best Regards,

    ttd

  • Hi ttd,

    I am happy you were able to figure out your SPI timing. Please let us know if you have any further questions.


    Best,

    Katlynne Jones