Hello,
Our board vendor asked us for the thermal plane void criteria? (For ADS1278MHFQ-MLS) Does TI have a recommended thermal plane void criteria?
Thanks,
Adam
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Hello,
Our board vendor asked us for the thermal plane void criteria? (For ADS1278MHFQ-MLS) Does TI have a recommended thermal plane void criteria?
Thanks,
Adam
Hi Adam,
I'm not sure what that is, but here is a document that goes into more depth about the powerpad and recommended soldermask: https://www.ti.com/lit/an/slma002h/slma002h.pdf
Best,
Zak
Hi Zak,
I am referring to the minimum solder joint area of the thermal pad. On Page 12, TI recommends a minimum solder joint are of 50% and a thermal model plot was given. On one of our boards, X-ray shows that the solder joint area of ADS1278MHFQ-MLS’s thermal pad is about 40-45%. We would like to know if 40-45% is an acceptable coverage for ADS1278MHFQ-MLS. How much is the change in thermal resistance between 40% and 50%? Would it possible for TI to rerun the thermal model for ADS1278MHFQ-MLS and plot the thermal resistance vs coverage like the ones on Page 12?
Thanks,
Adam
Hi Adam,
I believe that 40-45% is sufficient. We generally give err on the side of conservative recommendations and as long as they have a good stencil and sufficient thermal vias there shouldn't be any issues. Of course if they have any concerns then they could verify this by running the part in high speed mode at max data rate and monitoring the temperature increase of the IC.
Best,
Zak