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ADS122C04: Use for interleaved sampling of multiple channels

Brian Gestner
Prodigy 60 points
Part Number: ADS122C04
We are considering using the ADS122C04IPWR for the following system:
  1. Three analog channels that have a bandwidth of < 40 Hz with common reference channel
  2. Single ADS122C04IPWR for measuring the three differential analog channels (where negative side is common reference).
  3. Interleaved sampling of the three analog channels by using the 1000 Hz data rate setting, providing effectively ~333 Hz data rate per channel (Likely lower given there is no auto-sequencing and therefore I2C transactions are required).
Our concern: It seems for a given channel, the above acquisition scheme is equivalent to sampling a single channel for the 1000 Hz data rate setting followed by downsampling by a factor of 3. To prevent aliasing, the signal to be downsampled must not have energy above 166.66 Hz For the 1000 Hz data rate setting, however, the filter selected has a bandwidth of 483.8 Hz. As a result, the quantization/thermal noise between 166.66 Hz and 483.8 Hz will fold over and degrade resolution.
Questions
  1. Is this a valid concern (Perhaps we misunderstand the datasheet)?
  2. Is there an alternative configuration of the ADS122C04IPWR that we could use?
  3. Is there a more suitable part for out system?
 
Thank you!
  • 0
    TI__Guru** 112895 points

    Hi Brian,

    Welcome to the E2E forum!  The ADS122C04 is a Delta-Sigma oversampling device sampling at the modulator rate.  In normal mode the modulator runs at 256kHz.  The oversampling pushes the quantization noise to the higher frequencies and the digital filter acts as a lowpass filter removing this noise.

    As the modulator as running much faster than the data output rate, the antialiasing filter can be greatly relaxed.  If you have an aggressive analog filter you have to take into account the settling of the filter and response time.  So you would normally design the input filter to be a compromise.  You can refer to section 9.1.4 in the datasheet.

    If you need the I2C interface, this would be the best device to use.  The ADS122C04 is single-cycle settling for the digital filter, so as soon as one conversion completes the data are valid.  Here I would suggest that you use single-shot mode and monitor the DRDY output to signal when conversion is complete.  As soon as DRDY transitions from high to low, use an interrupt drive system to read the data and setup up the next mux channel, then send the Start/Sync command to start the next conversion.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 60 points

    Hi Bob,


    Thank you for the information.


    1. About 9.1.4 - Yes, we love the benefit of sigma delta ADCs in general. It's great that we only need to have a relatively simple (and low settling time) filter since the signal is sampled by the modulator clock. In this case, however, any energy that was in the original signal from 166.66 Hz to 483.8 Hz (roughly) will alias. Are you suggesting that we consider lowering the cutoff of this passive filter to something closer to 166.66 Hz?


    2. Let's assume that we make this filtering change and (hopefully) the settling time change is still acceptable. The sigma delta modulator itself will introduce shaped quantization noise. Normally as we lower the data rate, we are reducing the bandwidth and removing (ok, greatly attenuating to negligible levels) this quantization noise. If we use channel multiplexing in an interleaved fashion, however, it seems that we leave a window of this quantization noise present (166.Hz to 483.8 Hz) that then interferes completely through our passband as the result of the effective downsampling. Is this something that is just accepted when using a delta sigma modulator in this multiplexed configuration?


    3. Thanks for the configuration information. Is there any concern about continuously cycling the device in and out of low power mode? Is the time required to move from low power to full power relatively consistent for a given temperature? Lastly, we were actually considering using continuous conversion mode. We would start the conversion process initially. Then we would sequentially repeat writing the configuration 0 register with the new mux setting (which restarts the conversion), readback the previous result, and wait a predefined time depending on the sample rate (conversion time + margin). Of course, the very first sample in this sequence will be garbage.


    Thanks!
    Brian

  • +1 in reply to Brian Gestner
    TI__Guru** 112895 points

    HI Brian,

    Brian Gestner said:
    1. About 9.1.4 - Yes, we love the benefit of sigma delta ADCs in general. It's great that we only need to have a relatively simple (and low settling time) filter since the signal is sampled by the modulator clock. In this case, however, any energy that was in the original signal from 166.66 Hz to 483.8 Hz (roughly) will alias. Are you suggesting that we consider lowering the cutoff of this passive filter to something closer to 166.66 Hz?

    Yes, it is possible for the signal to alias.  As I know nothing about the sensor you are measuring, it is difficult for me to predict the outcome.  But usually noise that is aliased is from external sources with most types of sensors connected  to to the ADS122C04 as opposed to sensor noise itself.  Even with a cutoff of 1kHz, the 1st order filter roll-off is quite significant at the aliased frequency.  The combined affect of the analog filter and digital filter places the alias at a point where it is insignificant with respect to the ADC noise floor.  Certainly you can make the filter as aggressive as you want it to be.

    Brian Gestner said:

    2. Let's assume that we make this filtering change and (hopefully) the settling time change is still acceptable. The sigma delta modulator itself will introduce shaped quantization noise. Normally as we lower the data rate, we are reducing the bandwidth and removing (ok, greatly attenuating to negligible levels) this quantization noise. If we use channel multiplexing in an interleaved fashion, however, it seems that we leave a window of this quantization noise present (166.Hz to 483.8 Hz) that then interferes completely through our passband as the result of the effective downsampling. Is this something that is just accepted when using a delta sigma modulator in this multiplexed configuration?

    Each time you switch the input channels the conversion flushes the digital filter and restarts the conversion when operating in continuous conversion mode.  In single-shot mode the conversion starts at the point of the decode of the START/SYNC command which again flushes the digital filter.  Each conversion period is single-cycle settled and therefore fully valid regardless of the previous conversion.

    Brian Gestner said:

    3. Thanks for the configuration information. Is there any concern about continuously cycling the device in and out of low power mode? Is the time required to move from low power to full power relatively consistent for a given temperature? Lastly, we were actually considering using continuous conversion mode. We would start the conversion process initially. Then we would sequentially repeat writing the configuration 0 register with the new mux setting (which restarts the conversion), readback the previous result, and wait a predefined time depending on the sample rate (conversion time + margin). Of course, the very first sample in this sequence will be garbage.

    I suggested the single-shot mode mostly to simplify keeping track of the conversion data without the use of a timer.  You certainly can use the method you describe with continuous mode.

    Best regards,

    Bob B