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ADC12DJ5200RF: Impact of high offset spurious on the sampling clock jitter and ENOB

Benedikt Gerber
Prodigy 20 points
Part Number: ADC12DJ5200RF
Other Parts Discussed in Thread: ADC12J4000

Hi,

I am planning to use the ADC12DJ5200RF with a 3.1696 GHz sampling clock.

I found that I can use the formulas give in the ADC12J4000 Datasheet to calculate jitter requirements depending on frequency and desired ENOB.

I am wondering if there is an upper limit to which offset-frequency one should integrate the phase noise of the sampling clock in order to measure the jitter.

In my particular example, I have a clock signal with fairly strong spurious emissions at higher frequency offsets (measurement results are shown below). I will lower those with additional filtering but I am still wondering to which extend this is necessary and how these spurious would affect the ENOB. (Does the clock input of the ADC12DJ5200RF f.e. have a higher cut-off frequency from which spurious emissions no longer need to be considered?)

Thanks and kind regards!

Measurement results:

Some highlights:

Frequency offset Power Jitter
792.43 MHz -52.69dBc 164.69fs
1.58 GHz -50.06dBc 223.02fs
3.17 GHz -57.29dBc 97.01fs
7.92 GHz -51.57dBc 187.43fs

  • 0
    TI__Mastermind 20130 points

    Hi Benedikt,

    So far that I know, there is no industry standard for the upper limit when determining phase noise. I typically advise Fs/2.

    The 5200RF ADC clock inputs are very high in frequency in order to capture a fast slewing clock edge. As you are suggesting, it is best to filter the clock prior to the inputs. Otherwise, the noise and spurious omissions will convolve to the ADCs output spectrum and degrade the performance. 

    Regards,

    Rob