ADS1284: calibration

Hello bao huang,

Let me see if I can answer your questions directly.

How to setup the registers OFFSET[1:0] before and after the OFFSET calibration, FSC calibration?

As a reminder, the OFFSET[1:0] bit fields have a separate function compared to the OFSCAL[2:0] and GANCAL[2:0] (and by extension the FSC[2:0] register.

The OFFSET register is only used to get rid of idle tones (which can be viewed in the FFT of the output when no or a small input is applied). This offset is applied to the modulator input, and after the PGA inputs, which shifts the Full Scale Range (FSR).

In the case of an offset calibration, this is willfully added DC error. When we do a offset calibration, we’re trying to identify the DC error found in the PGA and the rest of the front end stage. So, if you enable the OFFSET, you’re mixing the error of the PGA with the error introduced by OFFSET, both of which can be corrected. As a result, you should enable this feature and then run the OFSCAL sequence.

Each time it runs with dfferent results. Could you please help to check the code as bellow?

Section 8.4.13 covers the “puesdo code” for calibration. I don’t think your code posted but if it does not follow this structure then it should be fixed.

I want to highlight that running calibration and getting different results is expected. Whether running the OFSCAL or GANCAL, there will be noise present. The calibration in the devices only average 15 times before updating the result in the FCS register. The calibration routine can be run multiple times and the FCS can be averaged to get a more consistent calibration result, as shown in the datasheet excerpt above.

For context, the noise floor is reduced by the inverse of sqrt(n) where n is the number of averages taken. So the more averages taken, the more it will cancel out the noise and eventually converge to the expected error of interest.

Best,

-Cole

Hello Bao Huang,

A couple of things are standing out based on your description. In general, we can get datasheet specifications in the table you've shown on our EVM. So this means:

• The test set up is not correct
• There are settings or other configurations that are make the testing set up different than the datasheet tests (which you suggested)
• The PCB, system, or environment is different that the tests which are contributing to more noise (which you suggested)
  • This includes a noisy reference voltage, PCB layout, and any noise contributed by input circuitry

Overview on the test:

We noticed you didn't provide any data or FFT that showed how you achieved the noise levels that were calculated. For context, the table you linked was derived in a similar manner to the test conditions given above. Note, the bipolar supplies and reference voltage, as well as the low power mode, OFFSET enabled, CHOP and your same data rate of 1000 SPS. As you can see, Figure 3 is very similar to your test condition, if not, please list the differences and configure the device in this set up to see if you can match the datasheet performance.

By simply using the equation given in the datasheet we can convert SNR to input referred noise:

Doing some quick math for Figure 3:

• SNR/20 = log(FSR/N)
• FSR/N = 10^(SNR/20)
• FSR/10^(SNR/20) = N
• (VREF/(2*sqrt(2)*PGA))/(10^(SNR/20) = N
• (5/(2*sqrt(2)*1))/(10^(123.7/20) = N
• N_RMS = 1.55 uV_RMS

Which is around the 1.6 uV_RMS given in the table.

So, if you cannot get a similar SNR value, one of the bullets I listed above are true.

Test set up:

There's nothing too special here. The inputs should be shorted to the same voltage, and a mid supply common mode voltage should be applied. This would mean a AINPx and AINNx would be tied to the same potential and then somehow connected to GND (which is (AVDD+AVDD)/2).

Setting MUX[2:0] will connect the inputs together internally through 400 ohm resistors. Otherwise, you could try to short the inputs externally, which could degrade performance, be cautious shorting them externally.

Settings:

There doesn't seem to be anything that you've listed that would contribute to differences in the noise measurements. I suggest you review the test conditions I showed for the datasheet plot. If you are using unipolar supplies, do not worry as it shouldn't affect performance if the test set up is used so that the inputs are shorted to the correct common mode voltage (e.g. AVDD = 5V and AVSS = 0V, then VCM = 2.5V).

PCB or other factors:

Feel free to share the schematic, I don't think we need to review layout yet. Note, that a noisy reference is usually the problem in situations where everything else is done correctly. Please review the noise specs on the reference used in the system. Note, we used the REF5050 in our testing.

Best,

-Cole

Hello Bao Huang,

1. The data recorded is always very noisy at the beginning with input connected to a 100Ω resistor, as high as maybe 1000uV， and after about 40 seconds the noise is get back to normal as the specification, does the AD need some time to be stabilized?

This isn't enough information to tell me about what kind of voltage you're putting in the inputs, the circuitry on the inputs, and your test steps are. For example what is 100 ohms--in series or parallel? What about your filter? What is 1000uV noise--RMS or peak to peak? As a result, I'll have to make a couple of assumptions to answer this.

While I see what you mean with flicker noise, this doesn't look like flicker noise to me (especially since chopping inputs theoretically have no 1/f noise). This looks more like the FFT for an RC charging circuit with a DC input. If you could monitor the input voltage and compare it to the data you've collected here (which we are going to assume is the output of the ADC), we would expect that you are applying a DC signal. However, the DC signal does not reach its target voltage until much much later, which the FFT is capturing. In short, this looks like a settling problem. Try to see if you can find what voltage in the system is not settled.

Alternatively, if you are trying to capture data directly after powering up the ADC, this could be the RC of the reference voltage needing to settle. This sometimes happens if there's an RC filter on the reference that needs to charge up. 

I will say, 40 seconds is a really long time to wait for anything to settle. I mean 100s of uF of capacitance type RC response. So if you have not verified that your system is stable by the time you are taking the measurement, I would highly recommend you verify that.

2. The measured voltage is always about 1.06 of the signal input, we didn't perform the FSC calibration.

Again, I have no information on your schematic or input circuitry, as well as you test conditions or the value of the voltage input.

We are making the assumption that you mean the measure value of ADC is always 106% of the original signal given.

One thing that comes to mind is the OFFSET and the offset of your system if you have not done calibration. 75mV might not matter to a full scale signal, but might be significant if you have a 1V input. In addition, we do expect gain error from the device so we don't know what your contribution is there to the final error seen at the output.

Its recommended that you measure your offset first. Similar to the noise test, tying the inputs together at a mid scale common mode voltage, you should be able to average the noise out of the measurements to see what the final voltage settles to. This will give you some idea of the offset voltage (by effectively giving a 0V input signal and what value is seen on the output of the ADC) and how that compares to your original test.

Final Thoughts 

I will also acknowledge that Seismic devices like this don't have comparatively good DC performance and are mostly used for AC signals (and are AC coupled at the inputs). If you have a decent sine generator, its pretty easy to see if you're getting performance you expect by calculating the RMS voltage expected from the output codes. If you would like to explain what you are trying to test, we might be able to give some advice.

Best,

-Cole