Other Parts Discussed in Thread: LMK04832
We have used LMK04832NKDT for generation of JESD204B clocks and sampling clocks for DACs and Xilinx MPSoC PL MGT.
Schematic design has been attached, please provide your feedback.
Design use details:
- All DACCLKP/N - AC coupled, LVPECL, 2520MHz
- MGTREFCLKnP/N - In the range of 150 - 200MHz
- PL_LMK_DEVCLK_P/N - In the range of 150 - 200MHz
- PL_LMK_SYSREF_P/N - In the range of 10 - 20MHz
- All SYSREFP/N - Set as per lane rate and system clock frequencies, AC coupled and option for DC coupling, LVPECL(AC coupled) LCPECL (DC coupled), <20MHz
- LMK Clock In 1 - 360MHz
- LMK Clock In 0 - 360MHz