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ADS1258-EP: External Clock Input Jitter Requirements

Danielle Demmon
Prodigy 20 points
Part Number: ADS1258-EP
Other Parts Discussed in Thread: ADS1258

Hello,

What are the specific jitter requirements for the ADS1228-EP's external clock input? The datasheet only says, "Make sure to use a clock source clean from jitter or interference;" I was hoping you all could provide more specific requirements. I'd like to use my FPGA's PLL output as the external clock source, but it has a worst case jitter of 2.5% × clock period peak-to-peak period, so I'm not sure if that's "clean" enough for this ADC. Thanks!

Cheers, Danielle  

  • 0
    TI__Mastermind 35141 points

    Hi Danielle,

    There are no specific jitter requirements for the ADS1258 because this depends on the performance level necessary for your system. That statement in the datasheet is more of a general recommendation, or a best practice, which is why it is not easily quantifiable.

    However, the link below is for an e-book that, among other things, discusses how clock jitter can manifest itself as noise. Specifically check out Chapter 5 and see if this helps answer your question.

    https://www.ti.com/lit/eb/slyy192/slyy192.pdf

    -Bryan